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For the Inventor, By the Inventor

Portland, OR, United States of America

Scott E Thompson

This inventor holds 14 USPTO granted patents. Top assignee: Intel Corporation. Active years: 1999-2011.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Scott E Thompson. Retrieved from https://idiyas.com/inventor/scott-e-thompson-vjvuf6ar

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 14

% Patents Active = 78.6

Average Co-Inventor Count = 3.2

ph-index = 9

Forward Citations = 229(Granted Patents)


Company Filing History:

goldMedal14 out of 56,290 
 
Intel Corporation
 patents

Years Active: 1999-2011

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14 patents (USPTO):Explore Patents
1. 7888710 - CMOS fabrication process utilizing special transistor orientation (2011-02-15),
2. 7312485 - CMOS fabrication process utilizing special transistor orientation (2007-12-25),
3. 7226824 - Nitrogen controlled growth of dislocation loop in stress enhanced transistor (2007-06-05),
4. 7187057 - Nitrogen controlled growth of dislocation loop in stress enhanced transistor (2007-03-06),
5. 6800887 - Nitrogen controlled growth of dislocation loop in stress enhanced transistor (2004-10-05),
6. 6624032 - Structure and process flow for fabrication of dual gate floating body integrated MOS transistors (2003-09-23),
7. 6515351 - Integrated circuit with borderless contacts (2003-02-04),
8. 6392271 - Structure and process flow for fabrication of dual gate floating body integrated MOS transistors (2002-05-21),
9. 6294823 - Integrated circuit with insulating spacers separating borderless contacts from the well (2001-09-25),
10. 6228777 - Integrated circuit with borderless contacts (2001-05-08),
11. 6020244 - Channel dopant implantation with automatic compensation for variations (2000-02-01),
12. 5976939 - Low damage doping technique for self-aligned source and drain regions (1999-11-02),
13. 5877072 - Process for forming doped regions from solid phase diffusion source (1999-03-02),
14. 5874344 - Two step source/drain anneal to prevent dopant evaporation (1999-02-23),

Title: The Innovations of Scott E. Thompson in Semiconductor Technology

Introduction

Scott E. Thompson, an accomplished inventor based in Portland, OR, has made significant contributions to the semiconductor industry with a total of 14 patents. His work primarily focuses on enhancing the efficiency and effectiveness of complementary metal oxide semiconductor (CMOS) technologies. As a member of Intel Corporation, Scott continues to drive innovation in this competitive field.

Latest Patents

Among his latest inventions are innovative CMOS fabrication processes that utilize special transistor orientations. These patents describe methods where complementary metal oxide semiconductor transistors are formed on a silicon substrate with a {100} crystallographic orientation. The transistors ensure that current flows in the channels parallel to the <100> direction, while additionally applying longitudinal tensile stress to the channels. This approach aims to enhance the performance of semiconductor devices, a critical factor in modern electronics.

Career Highlights

Scott E. Thompson's career at Intel Corporation has been marked by his relentless pursuit of innovation. With 14 patents under his name, he has established himself as a key player in the field of semiconductor research. His work has not only contributed to Intel's product line but has also helped in setting industry standards for CMOS technology.

Collaborations

Throughout his career, Scott has collaborated with notable peers such as Paul A. Packan and Mark Armstrong. Working alongside these talented individuals, he has contributed to groundbreaking projects and advancements in semiconductor technology, illustrating the importance of teamwork and collaboration in driving innovation.

Conclusion

Scott E. Thompson exemplifies the spirit of innovation within the semiconductor industry. Through his numerous patents and work at Intel Corporation, he continues to advance the field and inspire the next generation of inventors and engineers. His commitment to improving CMOS technologies highlights the vital role inventors play in shaping the future of electronics.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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