The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 05, 2007
Filed:
Aug. 13, 2004
Cory E. Weber, Hillsboro, OR (US);
Mark Armstrong, Portland, OR (US);
Harold Kennel, Beaverton, OR (US);
Tahir Ghani, Portland, OR (US);
Paul A. Packan, Beaverton, OR (US);
Scott Thompson, Portland, OR (US);
Cory E. Weber, Hillsboro, OR (US);
Mark Armstrong, Portland, OR (US);
Harold Kennel, Beaverton, OR (US);
Tahir Ghani, Portland, OR (US);
Paul A. Packan, Beaverton, OR (US);
Scott Thompson, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Known techniques to improve metal-oxide-semiconductor field effect transistor (MOSFET) performance is to add a high stress dielectric layer to the MOSFET. The high stress dielectric layer introduces stress in the MOSFET that causes electron mobility drive current to increase. This technique increases process complexity, however, and can degrade PMOS performance. Embodiments of the present invention create dislocation loops in the MOSFET substrate to introduce stress and implants nitrogen in the substrate to control the growth of the dislocation loops so that the stress remains beneath the channel of the MOSFET.