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For the Inventor, By the Inventor

Capistrano Beach, CA, United States of America

Saul Barajas

This inventor holds 17 USPTO granted patents, primarily in Cache Memory Systems. Top assignee: Unisys Corporation. Active years: 1992-2000.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Saul Barajas. Retrieved from https://idiyas.com/inventor/saul-barajas

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 17

% Patents Active = 100.0

Average Co-Inventor Count = 2.9

ph-index = 8

Forward Citations = 196(Granted Patents)


Location History:

  • Capistrano Beach, CA (US) (1992 - 1996)
  • Mission Viejo, CA (US) (1996 - 2000)

Company Filing History:

goldMedal17 out of 2,444 
 
Unisys Corporation
 patents

Years Active: 1992-2000

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Areas of Expertise:
Cache Memory
Invalidation Queue
Fault Tolerance
Inter-Processor Communication
Bit-Sliced Architecture
Virtual Pin Multiplier
Bus Arbitration
VLSI Gate Arrays
Combinatorial Logic
Programmable Logic
Data Bus
Cache Invalidation
17 patents (USPTO):Explore Patents
1. 6070166 - Apparatus and method for compressing a plurality of contiguous addresses (2000-05-30),
2. 5991853 - Methods for accessing coincident cache with a bit-sliced architecture (1999-11-23),
3. 5689680 - Cache memory system and method for accessing a coincident cache with a (1997-11-18),
4. 5642486 - Invalidation queue with 'bit-sliceability' (1997-06-24),
5. 5598551 - Cache invalidation sequence system utilizing odd and even invalidation (1997-01-28),
6. 5561773 - Programmable, multi-purpose virtual pin multiplier (1996-10-01),
7. 5553263 - Cache memory system with fault tolerance having concurrently operational (1996-09-03),
8. 5553259 - Apparatus and method for synchronizing the simultaneous loading of cache (1996-09-03),
9. 5506967 - Storage queue with adjustable level thresholds for cache invalidation (1996-04-09),
10. 5459836 - Inter-processor communication net (1995-10-17),
11. 5418935 - Apparatus for preventing double drive occurrences on a common bus by (1995-05-23),
12. 5321814 - System for optional module detection and reconfiguration (1994-06-14),
13. 5146596 - Multiprocessor multifunction arbitration system with two levels of bus (1992-09-08),
14. 5117132 - Flexible utilization of general flip-flops in programmable array logic (1992-05-26),
15. 5087953 - Flexible gate array system for combinatorial logic (1992-02-11),

Title: The Innovative Mind of Saul Barajas

Introduction

Saul Barajas is a prominent inventor based in Capistrano Beach, California. He has made significant contributions to the field of technology, particularly in the area of data storage and cache architecture. With a total of 17 patents to his name, Barajas continues to push the boundaries of innovation.

Latest Patents

Among his latest patents is an "Apparatus and method for compressing a plurality of contiguous addresses." This method focuses on efficiently compressing multiple addresses for storage in a queue. It involves recognizing individual addresses and block addresses, allowing for optimized data transfer and storage. Another notable patent is "Methods for accessing coincident cache with a bit-sliced architecture." This invention enhances performance by utilizing dual TAG RAM structures and invalidation queues, enabling overlapping processor and invalidation operations.

Career Highlights

Saul Barajas is currently employed at Unisys Corporation, where he applies his expertise in technology and innovation. His work has significantly impacted the efficiency of data processing and storage solutions.

Collaborations

Throughout his career, Barajas has collaborated with notable colleagues, including Bruce Ernest Whittaker and David M. Kalish. These partnerships have fostered a creative environment that encourages the development of groundbreaking technologies.

Conclusion

Saul Barajas exemplifies the spirit of innovation through his numerous patents and contributions to technology. His work continues to influence the industry, paving the way for future advancements.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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