The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 11, 1992
Filed:
Oct. 05, 1990
Applicant:
Inventors:
Bruce E Whittaker, Mission Viejo, CA (US);
Saul Barajas, Capistrano Beach, CA (US);
Assignee:
Unisys Corporation, Blue Bell, PA (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
357 40 ; 357 45 ; 357 41 ; 357 68 ; 357 74 ;
Abstract
A method and technique for inserting additive logic into the architecture of a gate array chip package whereby spare input and output pins can later be used to alter the logic functions by either disabling or enabling certain logic units internal to the chip by external signal injection.
Quick Actions:
Whittaker, Bruce. (1992). Flexible gate array system for combinatorial logic (U.S. Patent No. 5087953). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5087953
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile