The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 18, 1997
Filed:
Jul. 15, 1993
Applicant:
Inventors:
Bruce E Whittaker, Mission Viejo, CA (US);
David M Kalish, Laguno Niguel, CA (US);
Saul Barajas, Mission Viejo, CA (US);
Assignee:
Unisys Corp., Blue Bell, PA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ; G06F / ; G06F / ;
U.S. Cl.
CPC ...
395454 ; 364D / ; 36424341 ; 36496433 ; 36494392 ; 36424344 ; 36518902 ; 36523002 ; 395447 ; 395456 ; 395481 ;
Abstract
A 'bit-sliced' construction cache module dictates dual TAG RAM Structures and dual invalidation queues, yielding enhanced performance: putting half the TAG array in each of two cache arrays, and allowing each to handle only one-half of the possible address values. Preferably, one half-module handles ZERO least-significant bits and the other handles ONE least-significant bits. Processor operations and invalidation operations can be 'overlapped', and even operate simultaneously.