The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 26, 1992
Filed:
Feb. 08, 1991
Applicant:
Inventors:
Leland E Watson, Mission Viejo, CA (US);
Saul Barajas, Capistrano Beach, CA (US);
Bruce E Whittaker, Mission Viejo, CA (US);
Assignee:
Unisys Corporation, Blue Bell, PA (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
307465 ; 307480 ; 3072722 ;
Abstract
A programmable array logic unit (PAL) having a disconnected array of gates, inverters and D-Type flip-flops, is utilized by burning-in the interconnections, to enable the D flip-flops to function as J-K flip-flops and/or toggle flip-flops to enable flexibility in the functions available for utilization, by providing inputs for Direct Set, Direct Clear and Hold.
Quick Actions:
Watson, Leland. (1992). Flexible utilization of general flip-flops in programmable array logic (U.S. Patent No. 5117132). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5117132
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile