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For the Inventor, By the Inventor

Hillsborough, CA, United States of America

Sau-Ching Wong

This inventor holds 14 USPTO granted patents. Top assignees: Altera Corporation, Sandisk Corporation, Multi Level Memory Technology. Active years: 1986-2003.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Sau-Ching Wong. Retrieved from https://idiyas.com/inventor/sau-ching-wong-t7sv2ree

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 14

% Patents Active = 100.0

Average Co-Inventor Count = 1.7

ph-index = 14

Forward Citations = 1,764(Granted Patents)


Company Filing History:

goldMedal8 out of 4,334 
 
Altera Corporation
 patents
silverMedal4 out of 1,339 
 
Sandisk Corporation
 patents
bronzeMedal2 out of 20 
 
Multi Level Memory Technology
 patents

Years Active: 1986-2003

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14 patents (USPTO):Explore Patents
1. 6558967 - Multi-bit-per-cell memory system with numbers of bits per cell set by testing of memory units (2003-05-06),
2. 6363008 - Multi-bit-cell non-volatile memory with maximized data capacity (2002-03-26),
3. 6317349 - Non-volatile content addressable memory (2001-11-13),
4. 6166938 - Data encoding for content addressable memories (2000-12-26),
5. 6157558 - Content addressable memory cell and array architectures having low (2000-12-05),
6. 6134141 - Dynamic write process for high bandwidth multi-bit-per-cell and (2000-10-17),
7. 4912342 - Programmable logic device with array blocks with programmable clocking (1990-03-27),
8. 4899070 - Bit line sense amplifier for programmable logic devices (1990-02-06),
9. 4899067 - Programmable logic devices with spare circuits for use in replacing (1990-02-06),
10. 4871930 - Programmable logic device with array blocks connected via programmable (1989-10-03),
11. 4864161 - Multifunction flip-flop-type circuit (1989-09-05),
12. 4774421 - Programmable logic array device using EPROM technology (1988-09-27),
13. 4713792 - Programmable macrocell using eprom or eeprom transistors for (1987-12-15),
14. 4617479 - Programmable logic array device using EPROM technology (1986-10-14),

Title: Innovations of Sau-Ching Wong in Memory Technology

Introduction

Sau-Ching Wong is a prominent inventor known for her significant contributions to memory technology. Based in Hillsborough, California, she holds 14 patents that showcase her innovative approach to enhancing memory systems. Her work focuses on maximizing data capacity and improving the efficiency of memory arrays.

Latest Patents

One of her latest patents is a multi-bit-per-cell memory system that allows the number of bits per cell to be set based on the testing of memory units. This manufacturing method enables memory arrays to be optimized for performance, ensuring that those capable of accurately writing, storing, and reading more bits per cell are configured to do so. Conversely, arrays that do not meet performance expectations are adjusted to store fewer bits, thereby salvaging the overall memory device. Another notable patent involves a multi-bit-cell non-volatile memory that similarly maximizes data capacity by adjusting the number of bits stored per cell for each memory array based on performance testing.

Career Highlights

Throughout her career, Sau-Ching Wong has worked with leading companies in the technology sector, including Altera Corporation and SanDisk Corporation. Her expertise in memory technology has positioned her as a key figure in the development of advanced memory solutions.

Collaborations

Sau-Ching has collaborated with notable professionals in her field, including Robert F. Hartmann and Hock-Chuen So. These collaborations have contributed to her innovative projects and advancements in memory technology.

Conclusion

Sau-Ching Wong's contributions to memory technology through her patents and career achievements highlight her role as a leading inventor in the field. Her innovative approaches continue to influence the development of efficient memory systems.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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