Programmable logic devices with spare circuits for use in replacing

Abstract

A programmable logic device having a plurality of word lines and a plurality of bit lines, each of which is programmably interconnectable to at least one of the word lines for producing on each bit line a signal which is a logical function of the signal or signals on the word line or lines to which that bit line is interconnected. The logic device further includes at least one spare word line and/or bit line for use in the event that one of the regular lines of the same kind in defective. When the spare line is to be used, the device is preprogrammed to automatically redirect all signals intended for the bad line to another line, thereby putting the spare line into use. The signals thus automatically redirected include both the signals used during program mode to selectively interconnect the word lines and bit lines and the data signals subsequently processed during normal operation of the device.