Forward Citations = 1,492

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4 inventors (with patents filed for the assignee):

Sau Ching Wong (18 out of 93 patents)

Hock C So (3 out of 48 patents)

Sau-Ching Wong (2 out of 14 patents)

4. Kimberley Johnsen (1 out of 1 patent)

20 patents: Sort by Forward Citations

1. 6914820 - Erasing storage nodes in a bi-directional nonvolatile memory cell (2005-07-05),

2. 6906951 - Bit line reference circuits for binary and multiple-bit-per-cell memories (2005-06-14),

3. 6882567 - Parallel programming of multiple-bit-per-cell memory cells on a continuous word line (2005-04-19),

4. 6856568 - Refresh operations that change address mappings in a non-volatile memory (2005-02-15),

5. 6826084 - Accessing individual storage nodes in a bi-directional nonvolatile memory cell (2004-11-30),

6. 6754128 - Non-volatile memory operations that change a mapping between physical and logical addresses when restoring data (2004-06-22),

7. 6747896 - Bi-directional floating gate nonvolatile memory (2004-06-08),

8. 6662263 - Sectorless flash memory architecture (2003-12-09),

9. 6614685 - Flash memory array partitioning architectures (2003-09-02),

10. 6570810 - Contactless flash memory with buried diffusion bit/virtual ground lines (2003-05-27),

11. 6558967 - Multi-bit-per-cell memory system with numbers of bits per cell set by testing of memory units (2003-05-06),

12. 6532556 - Data management for multi-bit-per-cell memories (2003-03-11),

13. 6522586 - Dynamic refresh that changes the physical storage locations of data in flash memory (2003-02-18),

14. 6480422 - Contactless flash memory with shared buried diffusion bit line architecture (2002-11-12),

15. 6466476 - Data coding for multi-bit-per-cell memories having variable numbers of bits per memory cell (2002-10-15),

Company Overview

Multi Level Memory Technology, based in San Jose, CA, specializes in advanced memory solutions that enhance data storage efficiency and performance. The organization focuses on developing innovative memory architectures that cater to the evolving needs of computing and data-intensive applications. By leveraging cutting-edge research in memory technology, the company aims to provide scalable and high-performance solutions that address the challenges faced in modern computing environments.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Oct 20 2026

20 Patents

#349 in San Jose, CA

#3,940 in California

#16,409 in US

#31,295 in the World

San Jose, CA, United States of America

Multi Level Memory Technology

Forward Citations = 1,492

4 inventors:

Sau Ching Wong (18 out of 93 patents)

Hock C So (3 out of 48 patents)

Sau-Ching Wong (2 out of 14 patents)

4. Kimberley Johnsen (1 out of 1 patent)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Multi Level Memory Technology. Retrieved from https://idiyas.com/company/multi-level-memory-technology

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]