Multi-bit-cell non-volatile memory with maximized data capacity

Abstract

A multiple-bit-per-cell memory includes multiple memory arrays, where the number of bits stored per cell is separately set for each of the memory arrays. Memory arrays that testing proves are accurate when writing, storing, and reading a larger number of bits per cell are set to store more bits per cell, and memory arrays that cannot accurately write, store, or read as many bits per cell are set to store fewer bits per cell. Accordingly, the setting of the numbers of bits per cell for the respective memory arrays can maximize the capacity of a memory when some arrays perform better than expected. When the memory arrays on average perform worse than expected, the setting of the numbers of bits per cell salvage the memory device even if the memory is unable to provide the total expected memory capacity. One implementation of the memory includes a register for the settings of the memory arrays and one or more analog/multi-level write and read circuits. One or more converters convert between the analog and digital signals where the digital signals contain a number of bits selected according to a memory array being accessed. A data buffer between the arrays and a data input/output interface collects data for conversion between the variable data sizes used in the memory and standard size data units input and output from the memory.