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For the Inventor, By the Inventor

Cary, NC, United States of America

Sarit Dhar

This inventor holds 9 USPTO granted patents and 1 published patent application and 4 EPO patents. Top assignees: Cree Gmbh, Auburn University. Active years: 2014-2018.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Sarit Dhar. Retrieved from https://idiyas.com/inventor/sarit-dhar

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 9 

% Patents Active = 100.0

 

Average Co-Inventor Count = 3.9

ph-index = 3

Forward Citations = 25(Granted Patents)


Location History:

  • Cary, NC (US) (2014 - 2016)
  • Auburn, AL (US) (2016)
  • Raleigh, NC (US) (2018)

Company Filing History:

goldMedal9 out of 2,307 
 
Cree Gmbh
 patents
silverMedal1 out of 414 
 
Auburn University
 patents
where one patent can have more than one assignee

Years Active: 2014-2018

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9 patents (USPTO):Explore Patents
1. 9984894 - Forming SiC MOSFETs with high channel mobility by treating the oxide interface with cesium ions (2018-05-29),
2. 9478616 - Semiconductor device having high performance channel (2016-10-25),
3. 9396946 - Wet chemistry processes for fabricating a semiconductor device with increased channel mobility (2016-07-19),
4. 9343540 - Transistors with a gate insulation layer having a channel depleting interfacial charge (2016-05-17),
5. 9312343 - Transistors with semiconductor interconnection layers and semiconductor channel layers of different semiconductor materials (2016-04-12),
6. 9269580 - Semiconductor device with increased channel mobility and dry chemistry processes for fabrication thereof (2016-02-23),
7. 9142662 - Field effect transistor devices with low source resistance (2015-09-22),
8. 9029945 - Field effect transistor devices with low source resistance (2015-05-12),
9. 8841682 - Transistors with a gate insulation layer having a channel depleting interfacial charge and related fabrication methods (2014-09-23),

Title: The Innovative Contributions of Sarit Dhar

Introduction

Sarit Dhar is a prominent inventor based in Cary, NC (US), known for his significant contributions to the field of semiconductor technology. With a total of nine patents to his name, he has made remarkable advancements in the development of high-performance semiconductor devices.

Latest Patents

One of Sarit Dhar's latest patents focuses on "Forming SiC MOSFETs with high channel mobility by treating the oxide interface with cesium ions." This innovative method involves providing an insulation layer on a semiconductor layer and diffusing cesium ions into the insulation layer from an external source. The resulting MOSFET exhibits increased inversion layer mobility, enhancing its overall performance. Another notable patent is for a "Semiconductor device having high performance channel." This invention details a method of fabricating Metal-Oxide-Semiconductor (MOS) devices, particularly Silicon Carbide (SiC) MOS devices. The design includes a SiC substrate and a surface diffused channel that significantly improves carrier mobility while maintaining a normally-off behavior.

Career Highlights

Sarit Dhar has worked with notable companies such as Cree GmbH and Auburn University, where he has further honed his expertise in semiconductor technology. His work has been instrumental in advancing the capabilities of semiconductor devices, making them more efficient and effective for various applications.

Collaborations

Throughout his career, Sarit has collaborated with esteemed colleagues, including Sei-Hyung Ryu and Anant Kumar Agarwal. These partnerships have contributed to the innovative research and development of cutting-edge semiconductor technologies.

Conclusion

Sarit Dhar's contributions to the field of semiconductor technology through his patents and collaborations highlight his role as a leading inventor. His work continues to influence the development of high-performance devices that are essential in today's technology-driven world.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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