The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 23, 2014

Filed:

Aug. 27, 2009
Applicants:

Sarit Dhar, Cary, NC (US);

Sei-hyung Ryu, Cary, NC (US);

Inventors:

Sarit Dhar, Cary, NC (US);

Sei-Hyung Ryu, Cary, NC (US);

Assignee:

Cree, Inc., Durham, NC (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/161 (2006.01); H01L 21/04 (2006.01); H01L 29/78 (2006.01); H01L 29/16 (2006.01); H01L 29/66 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66068 (2013.01); H01L 29/513 (2013.01); H01L 29/51 (2013.01); H01L 29/78 (2013.01); H01L 29/1608 (2013.01);
Abstract

A metal-insulator-semiconductor field-effect transistor (MISFET) includes a SiC layer with source and drain regions of a first conductivity type spaced apart therein. A first gate insulation layer is on the SiC layer and has a net charge along an interface with the SiC layer that is the same polarity as majority carriers of the source region. A gate contact is on the first gate insulation layer over a channel region of the SiC layer between the source and drain regions. The net charge along the interface between the first gate insulation layer and the SiC layer may deplete majority carriers from an adjacent portion of the channel region between the source and drain regions in the SiC layer, which may increase the threshold voltage of the MISFET and/or increase the electron mobility therein.


Find Patent Forward Citations

Loading…