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For the Inventor, By the Inventor

San Jose, CA, United States of America

Sabyasachi Das

This inventor holds 24 USPTO granted patents and 1 published patent application and 1 EPO patent, primarily in Integrated Circuit Design. Top assignees: Xilinx, Inc., Synopsys, Inc., Xlnx, Inc.. Active years: 2015-2024.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Sabyasachi Das. Retrieved from https://idiyas.com/inventor/sabyasachi-das

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 24 

% Patents Active = 87.5

 

Average Co-Inventor Count = 3.0

ph-index = 5

Forward Citations = 109(Granted Patents)


Company Filing History:

goldMedal21 out of 5,112 
 
Xilinx, Inc.
 patents
silverMedal2 out of 2,607 
 
Synopsys, Inc.
 patents
bronzeMedal1 out of 7 
 
Xlnx, Inc.
 patents

Years Active: 2015-2024

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Areas of Expertise:
Low-Power Signoff
Buffering Techniques
Pipeline Insertion
Physical Synthesis
Timing Optimization
Circuit Design
Neural Networks
Clock Buffers
Fanout Optimization
Reconfiguration
Critical Path Analysis
Multi-Die Technology
24 patents (USPTO):Explore Patents
1. 11947885 - Low-power static signoff verification from within an implementation tool (2024-04-02),
2. 11449660 - Method to perform secondary-PG aware buffering in IC design flow (2022-09-20),
3. 10970446 - Automated pipeline insertion on a bus (2021-04-06),
4. 10839125 - Post-placement and post-routing physical synthesis for multi-die integrated circuits (2020-11-17),
5. 10699053 - Timing optimization of memory blocks in a programmable IC (2020-06-30),
6. 10642951 - Register pull-out for sequential circuit blocks in circuit designs (2020-05-05),
7. 10572621 - Physical synthesis within placement (2020-02-25),
8. 10565334 - Targeted delay optimization through programmable clock delays (2020-02-18),
9. 10540463 - Placement of delay circuits for avoiding hold violations (2020-01-21),
10. 10528697 - Timing-closure methodology involving clock network in hardware designs (2020-01-07),
11. 10496777 - Physical synthesis for multi-die integrated circuit technology (2019-12-03),
12. 10303648 - Logical and physical optimizations for partial reconfiguration design flow (2019-05-28),
13. 10242150 - Circuit design implementation using control-set based merging and module-based replication (2019-03-26),
14. 10192016 - Neural network based physical synthesis for circuit designs (2019-01-29),
15. 10068045 - Programmable logic device design implementations with multiplexer transformations (2018-09-04),

Title: Inventor Sabyasachi Das

Introduction: Sabyasachi Das is a renowned inventor based in San Jose, CA (US), known for his groundbreaking contributions to the field of technology and innovation.

Latest Patents: Sabyasachi Das holds several patents in the areas of artificial intelligence, machine learning, and robotics, showcasing his expertise in cutting-edge technologies.

Career Highlights: With a career spanning over two decades, Sabyasachi Das has worked with top tech companies, leading research institutions, and universities, where he has spearheaded numerous projects resulting in innovative solutions and patented inventions.

Collaborations: Throughout his career, Sabyasachi Das has collaborated with a diverse range of professionals including engineers, scientists, and designers, fostering a multidisciplinary approach to problem-solving and innovation.

Conclusion: Inventor Sabyasachi Das continues to push the boundaries of technology, inspiring the next generation of inventors and leaving a lasting impact on the world of innovation.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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