Xilinx, Inc.

Synopsys, Inc.

Xlnx, Inc.

Sabyasachi Das

Zhiyong Wang

Ruibing Lu

Aaron Ng

Niyati Shah

Xiaojian Yang

Frederic Revenu

Renu Mehra

Sreesan Venkatakrishnan

Govinda Keshavdas

Wei Chen

Ilya K Ganusov

Khang Kim Dao

Jeffrey H Seltzer

Chaithanya Dudha

Kaushik De

Aman Gayasen

Rajat Aggarwal

KunMing Ho

Anup Kumar Sultania

Ben Mathew

Prabal Basu

Chiwei Huang

Ronald E Plyler

Lin Chai

Jin Wu

Maheshwar Chandrasekar

Godwin R Maben

David Allen

Meera Viswanath

In one aspect, a method includes invoking a signoff tool via a first command from an implementation tool running on a register transfer level (RTL) design, and executing a native command of the signoff tool from within the implementation tool. The native command generates a notification. The method also includes determining whether the RTL design passes a low-power signoff check based on the notification and sending the design for final signoff verification based on the determination that the RTL design passes the low-power signoff checks.

Low-power static signoff verification from within an implementation tool

A system to generate a design of an integrated circuit, the system comprising a memory and a processor, the processor to define a plurality of voltage area regions (VARs), based on an availability of one or more of a primary power source and one or more secondary power sources. The processor further to constrain placement and/or routing of an element in the design of the integrated circuit within a voltage area region of the plurality of voltage area regions defined by secondary power/ground (PG) constraints based on power requirements of the element.

Method to perform secondary-PG aware buffering in IC design flow

The disclosed approaches process a circuit design having first attributes associated with two or more signals or with sources of the two or more signals. The first attributes specify identifier values. The elements of the circuit design are placed on a target integrated circuit (IC), and timing analysis of the circuit design is performed after placing the elements of the circuit design. In response to the first attributes of the two or more signals or sources specifying equivalent identifier values and a path of at least one of the two or more signals or sources being timing-critical, equal numbers of one or more pipeline registers are inserted on paths of the two or more signals or sources.

Automated pipeline insertion on a bus

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for performing post-routing and post-placement physical synthesis optimizations. One of the methods includes receiving a circuit design of a multi-die integrated circuit (IC) device having a first die connected with a second die, wherein the circuit design specifies a respective initial component placement of each of a plurality of components on the first die and the second die. A first driver on the first die having a plurality of loads on the second die is selected. A transmit site is selected on the first die that reduces a distance between the first driver and a load of the plurality of loads on the second die. The circuit design is modified including moving the first driver to the selected transmit site on the first die.

Post-placement and post-routing physical synthesis for multi-die integrated circuits

Methods and apparatus for implementing a circuit design are provided. A physical description is generated corresponding to a predefined physical layout of a programmable integrated circuit. The circuit design includes a memory block. A timing analysis is executed to determine a first timing profile of the physical description. The physical description is optimized (or at least altered), and a physical implementation is generated based on the optimized physical description. Optimizing the physical description includes: selectively moving from or into the memory block of the physical description a register in response to an attribute of the memory block; executing a timing analysis to determine a second timing profile of the physical description with the register moved from or into the memory block of the physical description; comparing the first and second timing profiles; and selectively accepting or reversing the moving based on the comparison of the first and second timing profiles.

Timing optimization of memory blocks in a programmable IC

Register pull-out for sequential circuit blocks may include determining, using computer hardware, a net of a circuit design having a driver that is a macro circuit block driving a plurality of loads and determining, using the computer hardware, a placement difficulty of the net based upon a type of the driver and number and type of the plurality of loads. In response to determining that the placement difficulty of the net exceeds a threshold placement difficulty, the computer hardware is capable of modifying the circuit design by pulling a register from the driver to a location on a device external to the driver and changing internal logic of the driver based upon the pulled register.

Register pull-out for sequential circuit blocks in circuit designs

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for performing physical synthesis with an overall placement process. One of the methods includes receiving an initial netlist of a circuit design for an IC. A global placement process is performed that assigns to some components in the initial netlist a respective initial location on the IC. One or more physical synthesis processes are performed to generate a modified netlist before assigning a final location to all components in the circuit design by an overall placement process. A subsequent placement process is performed to assign a final location on the IC to all components in the modified netlist.

Physical synthesis within placement

Disclosed approaches for processing a circuit design include determining first slacks of cells, including a target cell, coupled to receive a clock signal through a first clock leaf. The first slacks are based on a current delay value specified for a first programmable delay circuit. The method predicts second slacks of the cells based on another delay value specified for the first programmable delay circuit, and then determines whether or not the second slacks indicate a degradation in timing relative to the first slacks. The current delay value of the first programmable delay circuit is adjusted to the other delay value in response to determining the second slacks indicates no degradation in timing. The target cell is reconnected to receive the clock signal from a second clock leaf having a second programmable delay circuit specified with the other delay value in response to determining the second slacks indicates degradation in timing.

Targeted delay optimization through programmable clock delays

Disclosed approaches for processing a circuit design include identifying a driver and a load having a hold violation in the circuit design. The circuit design is targeted to an integrated circuit (IC) die. The method determines a first offset from a location on a perimeter of a rectangular region of the IC die having corners at locations of the driver and the load such that a length of a signal path from the driver through a first candidate location having placement coordinates that are outside the rectangular region and at the first offset from the location on the perimeter resolves the hold violation. The method determines availability of the first candidate location. In response to determining that the first candidate location is available, the method includes instantiating a delay circuit at the first candidate location and specifying connections that connect the delay circuit between the driver and the load.

Placement of delay circuits for avoiding hold violations

Embodiments disclosed herein describe techniques for moving nets between a source and a plurality of sinks in a design of an integrated circuit from a data network to a clock network. In one embodiment, the clock network propagates clock signals or timing signals throughout the integrated circuit while the data network transmits data signals between circuitry in the integrated circuit. In one embodiment, the clock network has a predefined number of clock signal nets which can be assigned to carry clock signals to circuit logic in the integrated circuit. However, some of the clock signal nets may be unused. In one embodiment, a design application identifies candidate sinks which have positive slack. If using the clock network to couple the sink to the source satisfies predetermined timing requirements, then the design change is committed.

Timing-closure methodology involving clock network in hardware designs

Physical synthesis for a circuit design can include determining, using a processor, a candidate net from a circuit design, wherein the candidate net spans a plurality of dies of a multi-die integrated circuit, and modifying, using the processor, the candidate net by performing physical synthesis resulting in a modified candidate net. The physical synthesis includes relocating a driver or a load of the candidate net or replicating the driver of the candidate net. An incremental routing can be performed on the modified candidate net using the processor. Further, the modified candidate net can be selectively committed using the processor based upon a timing analysis.

Physical synthesis for multi-die integrated circuit technology

Implementing a partial reconfiguration design flow can include determining an interface net connecting static circuitry and a first reconfigurable module of a circuit design, performing, using a processor, a logical optimization on first circuitry of the static circuitry that is entirely external to the first reconfigurable module and on second circuitry entirely within the reconfigurable module, and excluding the interface net from processing using the logical optimization.

Logical and physical optimizations for partial reconfiguration design flow

Circuit design implementation can include selecting a first and second load each having a control pin of a same type driven by a different driver, determining whether the driver of the first load matches the driver of the second load, and modifying the circuit design to drive the control pins of the first load and the second load using the driver of the first load. Circuit design implementation can include selecting a net having a driver and a plurality of loads exceeding a threshold, determining a selected module of the circuit design having a number of the plurality of loads of the net that meet a cloning criteria, and, in response, modifying the circuit design by creating a clone of the driver within the selected module and driving each load of the net within the selected module with the clone of the driver.

Circuit design implementation using control-set based merging and module-based replication

Physical synthesis for a circuit design can include determining, using a processor, features relating to a signal path of the circuit design not meeting a timing requirement, processing the features through a first neural network model using the processor, wherein the first neural network model is trained to indicate an effectiveness of a first physical synthesis optimization, and selectively performing, using the processor, the first physical synthesis optimization for the signal path based upon a result from the first neural network model.

Neural network based physical synthesis for circuit designs

A programmable logic design is generated for a programmable logic device (PLD) containing configurable logic blocks (CLBs) each having a plurality of multiplexers and look-up-table (LUT) circuits. A first subset of multiplexers are identified from the plurality of multiplexers based upon an analysis of design definitions for input signals of the plurality of multiplexers. The first subset of multiplexers are transformed into LUT logic. Configuration data is generated that is designed to be loaded into the PLD to configure the CLBs. The configuration data includes the LUT logic.

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San Jose, CA, United States of America

Sabyasachi Das