The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 28, 2019
Filed:
May. 19, 2017
Applicant:
Xilinx, Inc., San Jose, CA (US);
Inventors:
Sabyasachi Das, San Jose, CA (US);
Zhiyong Wang, Cupertino, CA (US);
Niyati Shah, San Jose, CA (US);
Assignee:
XILINX, INC., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 17/00 (2019.01); G06F 15/00 (2006.01); G06F 9/30 (2018.01); G06F 15/78 (2006.01); G06F 9/38 (2018.01); G06F 15/80 (2006.01); G06F 15/76 (2006.01);
U.S. Cl.
CPC ...
G06F 15/7867 (2013.01); G06F 9/3885 (2013.01); G06F 9/3897 (2013.01); G06F 15/8007 (2013.01); G06F 15/76 (2013.01); G06F 15/80 (2013.01); G06F 17/505 (2013.01); G06F 2015/761 (2013.01);
Abstract
Implementing a partial reconfiguration design flow can include determining an interface net connecting static circuitry and a first reconfigurable module of a circuit design, performing, using a processor, a logical optimization on first circuitry of the static circuitry that is entirely external to the first reconfigurable module and on second circuitry entirely within the reconfigurable module, and excluding the interface net from processing using the logical optimization.