IDiyas

For the Inventor, By the Inventor

Folsom, CA, United States of America

Robert L Baltar

USPTO Granted Patents = 14

Average Co-Inventor Count = 1.9

ph-index = 6

Forward Citations = 171(Granted Patents)


Location History:

  • El Dorado Hills, CA (US) (2003)
  • Folsom, CA (US) (1996 - 2017)

Company Filing History:

goldMedal12 out of 54,664 
 
Intel Corporation
 patents
silverMedal2 out of 37,905 
 
Micron Technology Incorporated
 patents

Years Active: 1996-2017

Loading Chart...
14 patents (USPTO):Explore Patents
1. 9710376 - Wear leveling for a memory device (2017-07-18),
2. 9104547 - Wear leveling for a memory device (2015-08-11),
3. 6744671 - Kicker for non-volatile memory drain bias (2004-06-01),
4. 6574141 - Differential redundancy multiplexor for flash memory devices (2003-06-03),
5. 6570789 - Load for non-volatile memory drain bias (2003-05-27),
6. 6535423 - Drain bias for non-volatile memory (2003-03-18),
7. 6456540 - Method and apparatus for gating a global column select line with address transition detection (2002-09-24),
8. 6446179 - Computing system with volatile lock architecture for individual block locking on flash memory (2002-09-03),
9. 6442069 - Differential signal path for high speed data transmission in flash memory (2002-08-27),
10. 6434049 - Sample and hold voltage reference source (2002-08-13),
11. 6212099 - Preventing data corruption in a memory device using a modified memory cell conditioning methodology (2001-04-03),
12. 6209069 - Method and apparatus using volatile lock architecture for individual block locking on flash memory (2001-03-27),
13. 5663923 - Nonvolatile memory blocking architecture (1997-09-02),
14. 5517138 - Dual row selection using multiplexed tri-level decoder (1996-05-14),
This text is generated by artificial intelligence and may not be accurate.
Please report any incorrect information to support@idiyas.com
Loading…