The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 18, 2017

Filed:

Jun. 29, 2015
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventor:

Robert Baltar, Folsom, CA (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 12/02 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0246 (2013.01); G11C 11/5628 (2013.01); G11C 16/0483 (2013.01); G11C 16/3495 (2013.01); G06F 2212/7211 (2013.01);
Abstract

Methods of operating a memory device are useful in managing wear leveling operations. Such methods include receiving an instruction from a host device in communication with the memory device, wherein the instruction comprises a command portion indicating a desire to identify portions of the memory device to be excluded from wear leveling operations and an argument portion comprising information identifying a particular group of one or more blocks of the plurality of blocks; storing the information identifying the particular group of one or more blocks to a non-volatile memory of the memory device as a portion of information identifying blocks to be excluded from wear leveling operations; and performing one or more wear leveling operations only on a subset of the plurality of blocks responsive to the information identifying blocks to be excluded from wear leveling operation.


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