The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 27, 2003
Filed:
Dec. 29, 2000
Applicant:
Inventors:
Ritesh Trivedi, Fair Oaks, CA (US);
Robert Baltar, Folsom, CA (US);
Mark Bauer, Placerville, CA (US);
Sandeep Guliani, Folsom, CA (US);
Balaji Srinivasan, Fair Oaks, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 1/606 ;
U.S. Cl.
CPC ...
G11C 1/606 ;
Abstract
An apparatus is disclosed for providing a load for a non-volatile memory drain bias circuit. Under an embodiment, a load for a non-volatile memory drain bias circuit comprises a column load and a current mirror, a reference voltage for the current mirror being a sample and hold voltage reference. The column load and the current mirror are coupled to a cascode device.
Quick Actions:
Trivedi, Ritesh. (2003). Load for non-volatile memory drain bias (U.S. Patent No. 6570789). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6570789
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