The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6456540 B1

PDF
Full Text
Expired
Date of Patent:
Sep. 24, 2002

Filed:

Jan. 30, 2001
Applicant:
Inventors:

Robert Baltar, Folsom, CA (US);

Ritesh Trivedi, Orangevale, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/00 ;
U.S. Cl.
CPC ...
G11C 7/00 ;
Abstract

A method and apparatus for a memory device is described. In one embodiment, global Y (GY) enable is gated by the trailing edge of a address transition detection (ATD) pulse. The ATD pulse ensures that the GY enable is off during periods when the memory device is not attempting to read a memory cell. The sense (SEN) node between the GY transistor and drain bias circuit may be charged up and global bit line (GBL) may be grounded. During this time, the power supply current is cut off by the GY transistor itself, thereby eliminating the need of separate cut-off transistors within the drain bias circuit. This permits minimal time delay in sensing after the incoming address is stable.


Find Patent Forward Citations

Baltar, Robert. (2002). Method and apparatus for gating a global column select line with address transition detection (U.S. Patent No. 6456540). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6456540

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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