Dallas, TX, United States of America

Richard P Rouse

This inventor holds 4 USPTO granted patents and 1 EPO patent. Top assignees: Cadence Design Systems, Inc., Texas Instruments Corporation. Active years: 2006-2012.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Richard P Rouse. Retrieved from https://idiyas.com/inventor/richard-p-rouse-ng3hckq2

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0


Average Co-Inventor Count = 2.2

ph-index = 3

Forward Citations = 49(Granted Patents)


Location History:

  • Dallas, TX (US) (2010)
  • Santa Clara, CA (US) (2006 - 2012)

Company Filing History:


Years Active: 2006-2012

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4 patents (USPTO):Explore Patents

Title: Richard P Rouse: Innovator in Integrated Circuit Design

Introduction

Richard P Rouse is a notable inventor based in Dallas, TX (US), recognized for his contributions to the field of integrated circuit design. With a total of 4 patents, Rouse has made significant advancements that enhance the performance and reliability of semiconductor devices.

Latest Patents

One of Rouse's latest patents focuses on the timing, noise, and power analysis of integrated circuits. This invention provides design for manufacturing (DFM) systems that incorporate manufacturing variations in the analysis of integrated circuits. It calculates predicted manufacturing variations on the shapes of interconnects and devices within the drawn layout of a circuit design. The shape variation on interconnects is converted to variations in resistor-capacitor (RC) parasitics, while the shape variation on devices translates to variations in device parameters. These variations ultimately affect timing performance, signal integrity, and power consumption. The results from these analyses are integrated back into the design flow as incremental delay files, noise failures, and leakage power hotspots.

Another significant patent by Rouse is related to the gate sidewall spacer and its method of manufacture. This invention outlines a method for manufacturing a semiconductor device, which includes providing a gate dielectric layer and a gate electrode layer over a substrate. The process involves forming a gate sidewall spacer along the sidewalls of the gate dielectric and electrode layers using a plasma-enhanced chemical vapor deposition process. Additionally, it introduces a local hydrogen treatment method to create different hydrogen concentrations in NMOS and PMOS sidewall spacers.

Career Highlights

Throughout his career, Richard P Rouse has worked with prominent companies such as Cadence Design Systems, Inc. and Texas Instruments Corporation. His experience in these organizations has contributed to his expertise in semiconductor technology and integrated circuit design.

Collaborations

Rouse has collaborated with notable professionals in the field, including Haizhou Chen and Li-Fu Chang. These collaborations have further enriched his work and innovations in integrated circuit technology.

Conclusion

Richard P Rouse stands out as an influential inventor in the realm of integrated circuits, with a focus on enhancing design methodologies and manufacturing processes. His patents reflect a deep understanding of the complexities involved in semiconductor technology, making significant contributions to the industry.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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