Texas Instruments Corporation

Cadence Design Systems, Inc.

Richard P Rouse

Nishath Verghese

Li-Fu Chang

Haizhou Chen

Haowen Bu

Shashank Sureshchandra Ekbote

DFM systems are provided that incorporate manufacturing variations in the analysis of integrated circuits by calculating predicted manufacturing variations on the shapes of interconnects and devices of the drawn layout of a circuit design. The shape variation on interconnects is converted to variations in resistor-capacitor (RC) parasitics. The shape variation on devices is converted to variations in device parameters. The variation in device parameters and wire parasitics is converted to changes in timing performance, signal integrity, and power consumption by determining the impact of device parameter and wire parasitic variations on the behavior of each instance of a standard cell. The results from these analyses are integrated back into the design flow as incremental delay files (timing), noise failures and buffer insertion/driver resizing commands (noise), and leakage power hotspots and cell substitution commands (power consumption).

Timing, noise, and power analysis of integrated circuits

The present invention provides a method for manufacturing a semiconductor device, a semiconductor device, and a method for manufacturing an integrated circuit including a semiconductor device. The method for manufacturing the semiconductor device, without limitation, may include providing a gate dielectric layer () and a gate electrode layer () over a substrate (), and forming a gate sidewall spacer () along one or more sidewalls of the gate dielectric layer () and the gate electrode layer () using a plasma enhanced chemical vapor deposition process, and forming different hydrogen concentration in NMOS and PMOS sidewall spacers () using a local hydrogen treatment (LHT) method.

Gate sidewall spacer and method of manufacture therefor

Modeling device variations in integrated circuit design

A technique for forming a MOS capacitor () that can be utilized as a decoupling capacitor is disclosed. The MOS capacitor () is formed separately from the particular circuit device () that it is to service. As such, the capacitor () and its fabrication process can be optimized in terms of efficiency, etc. The capacitor () is fabricated with conductive contacts () that allow it to be fused to the device () via conductive pads () of the device (). As such, the capacitor () and device () can be packaged together and valuable semiconductor real estate can be conserved as the capacitor () is not formed out of the same substrate as the device (). The capacitor () further includes deep contacts () whereon bond pads () can be formed that allow electrical connection of the capacitor () and device () to the outside world.

Wafer bonded MOS decoupling capacitor

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Dallas, TX, United States of America

Richard P Rouse