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For the Inventor, By the Inventor

San Diego, CA, United States of America

Ravi H Motwani

This inventor holds 60 USPTO granted patents and 12 published patent applications and 6 EPO patents, primarily in Non-Volatile Memory (CPC class H03M). Top assignees: Intel Corporation, Sk Hynix Nand Product Solutions Corp. (Dba Solidigm). Active years: 2013-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Ravi H Motwani. Retrieved from https://idiyas.com/inventor/ravi-h-motwani

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 60 

% Patents Active = 98.3

 

Average Co-Inventor Count = 1.7

ph-index = 6

Forward Citations = 270(Granted Patents)

Forward Citations (Not Self Cited) = 237(Dec 10, 2025)


Inventors with similar research interests:


Location History:

  • Santa Clara, CA (US) (2013 - 2014)
  • San Diego, CA (US) (2013 - 2020)
  • Fremont, CA (US) (2018 - 2024)

Company Filing History:

goldMedal59 out of 56,365 
 
Intel Corporation
 patents
silverMedal1 out of 19 
 
Sk Hynix Nand Product Solutions Corp. (Dba Solidigm)
 patents

Years Active: 2013-2025

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Areas of Expertise:
Error Correction
Data Scrambler
Memory Controllers
LDPC Codes
Latency Improvement
Bit Error Rate
Data Reliability
Soft Reads
Dynamic Data
Non-Uniform Scaling
Persistent Memory
Media Defects
60 patents (USPTO):Explore Patents
1. 12504912 - Soft read for NVM that is subject to destructive reads (2025-12-23),
2. 12339742 - Soft read operations with progressive data output (2025-06-24),
3. 12253911 - Programmable and high-performance data scrambler for non-volatile memory controllers (2025-03-18),
4. 12169435 - Dynamic self-correction of message reliability in LDPC codes (2024-12-17),
5. 12126361 - Techniques to improve latency of retry flow in memory controllers (2024-10-22),
6. 12113547 - Application of low-density parity-check codes with codeword segmentation (2024-10-08),
7. 12106815 - Variable error correction codeword packing to support bit error rate targets (2024-10-01),
8. 12032725 - Data scrambler for persistent memory (2024-07-09),
9. 12001280 - Overcoming error correction coding mis-corrects in non-volatile memory (2024-06-04),
10. 11777530 - Methods and apparatuses for generating optimized LDPC codes (2023-10-03),
11. 11657889 - Error correction for dynamic data in a memory that is row addressable and column addressable (2023-05-23),
12. 11515891 - Application of low-density parity-check codes with codeword segmentation (2022-11-29),
13. 11429469 - Defective bit line management in connection with a memory access (2022-08-30),
14. 11182240 - Techniques to improve error correction using an XOR rebuild scheme of multiple codewords and prevent miscorrection from read reference voltage shifts (2021-11-23),
15. 11159175 - Non-uniform iteration-dependent min-sum scaling factors for improved performance of spatially-coupled LDPC codes (2021-10-26),

Title: Innovations of Ravi H Motwani: A Pioneer in Data Technologies

Introduction

Ravi H Motwani, a prominent inventor based in San Diego, CA, has made significant contributions to the field of data technologies, holding an impressive portfolio of 58 patents. His innovative spirit and dedication to advancing technology have led to remarkable inventions that optimize data processing and error correction.

Latest Patents

Among his latest patents, Ravi has developed a "Programmable and high-performance data scrambler for non-volatile memory controllers." This invention outlines systems, apparatuses, and methods that generate a first set of scrambler bits based on a destination page number and create a second set of bits influenced by a programmable nonlinear function. The combination of these bits forms a scrambler seed that enables the randomization of data, enhancing storage efficiency in non-volatile memory systems.

Another noteworthy patent is focused on the "Dynamic self-correction of message reliability in LDPC codes." This innovation involves an electronic apparatus designed to detect unreliable messages during error correction operations. It assesses the degree of unreliability and adjusts the influence of these messages accordingly, ensuring higher data integrity through improved error correction effectiveness.

Career Highlights

Ravi's career boasts significant experience in esteemed organizations, including Intel Corporation. His work at Intel has showcased his ability to integrate cutting-edge technology and innovative ideas, driving advancements in data systems.

Collaborations

Throughout his career, Ravi has collaborated with talented professionals like Santhosh K Vanaparthy and Pranav Kalavade. Such partnerships have contributed to a collaborative atmosphere that fosters innovation and the exchange of ideas.

Conclusion

Ravi H Motwani's dedication to innovation in the realm of data technologies is evident through his numerous patents and collaborative efforts. With a strong foundation in electronic systems and a keen understanding of error correction, he continues to pave the way for future advancements in data processing.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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