The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 23, 2023
Filed:
Mar. 23, 2020
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Jawad B. Khan, Portland, OR (US);
Richard L. Coulson, Portland, OR (US);
Zion S. Kwok, Vancouver, CA;
Ravi H. Motwani, Fremont, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/42 (2006.01); G11C 29/44 (2006.01); G11C 11/409 (2006.01); G11C 5/02 (2006.01); G11C 29/02 (2006.01); G11C 29/12 (2006.01);
U.S. Cl.
CPC ...
G11C 29/42 (2013.01); G11C 5/025 (2013.01); G11C 11/409 (2013.01); G11C 29/021 (2013.01); G11C 29/44 (2013.01); G11C 2029/1204 (2013.01);
Abstract
Error correction values for a memory device include row error correction values and column error correction values for the same memory array. The memory device includes a memory array that is addressable in two spatial dimensions: a row dimension and a column dimension. The memory array is written as rows of data, and can be read as rows in the row dimension or read as columns in the column dimension. A data write triggers updates to row error correction values and to column error correction values.