The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 23, 2021
Filed:
Sep. 25, 2020
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Santhosh K. Vanaparthy, Santa Clara, CA (US);
Zion S. Kwok, Vancouver, CA;
Ravi H. Motwani, Fremont, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/10 (2006.01); H03M 13/21 (2006.01); H03M 13/29 (2006.01); H03M 13/00 (2006.01); H03M 13/11 (2006.01); H03M 13/39 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1016 (2013.01); H03M 13/1111 (2013.01); H03M 13/1177 (2013.01); H03M 13/21 (2013.01); H03M 13/2942 (2013.01); H03M 13/3927 (2013.01); H03M 13/617 (2013.01);
Abstract
Examples include techniques to improve error correction using an exclusive OR (XOR) rebuild scheme that includes two uncorrectable codewords. Examples include generation of soft XOR codewords using bits of correctable codewords to rebuild a codeword read from a memory that has uncorrectable errors and adjust bit reliability information to generate a new codeword having correctable errors. Examples also include techniques to prevent mis-correction due to read reference voltage shifts using non-linear transformations.