The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 30, 2022

Filed:

Mar. 08, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Ali Khakifirooz, Brookline, MA (US);

Pranav Kalavade, San Jose, CA (US);

Ravi H. Motwani, Fremont, CA (US);

Chang Wan Ha, San Ramon, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/07 (2006.01); G11C 16/34 (2006.01); G11C 7/12 (2006.01); G11C 16/14 (2006.01); G11C 29/44 (2006.01);
U.S. Cl.
CPC ...
G06F 11/076 (2013.01); G11C 7/12 (2013.01); G11C 16/14 (2013.01); G11C 16/3431 (2013.01); G11C 29/44 (2013.01);
Abstract

Examples herein relate to determining a number of defective bit lines in a memory region prior to applying a program or erase voltages. If a threshold number of bit lines that pass during a program or erase verify operation is used to determine if the program or erase operation passes or fails, the determined number of defective bit lines can be used to adjust the determined number of passes or fails. In some cases, examples described herein can avoid use of extra bit lines and look-up table circuitry to use in place of defective bit lines and save silicon space and cost associated with the use of extra bit-lines. In some examples, a starting magnitude of a program voltage signal can be determined by considering a number of defective bit lines.


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