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For the Inventor, By the Inventor

Bengaluru, India

Raja Prabhu J

This inventor holds 19 USPTO granted patents and 9 published patent applications and 1 EPO patent, primarily in Digital Signal Processing. Top assignees: Shaoxing Yuanfang Semiconductor Co., Ltd., Aura Semiconductor Pvt. Ltd, Shaoxing Yuanfang Semiconductor Co., Ltd.. Active years: 2017-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Raja Prabhu J. Retrieved from https://idiyas.com/inventor/raja-prabhu-j

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 19 

% Patents Active = 84.2

 

Average Co-Inventor Count = 5.0

ph-index = 2

Forward Citations = 16(Granted Patents)


Company Filing History:

goldMedal11 out of 21 
 
Shaoxing Yuanfang Semiconductor Co., Ltd.
 patents
silverMedal4 out of 10 
 
Aura Semiconductor Pvt. Ltd
 patents
bronzeMedal2 out of 2 
 
Shaoxing Yuanfang Semiconductor Co., Ltd.
 patents
4. 1 out of 7 
 
Ningbo Aura Semiconductor Co., Limited
 patents
5. 1 out of 7 
 
Ningbo Aura Semiconductor Co., Ltd
 patents

Years Active: 2017-2026

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Areas of Expertise:
Digital-To-Time Converter
Phase-Locked Loop
Time-To-Digital Converter
Fractional Frequency Dividers
Signal Calibration
Clock Jitter
Noise Reduction
Frequency Divider
Integrated Circuit
Counter Design
Output Frequency
Phase Difference
19 patents (USPTO):Explore Patents
1. 12732199 - Reducing non-linearity in a digital-to-time converter (DTC) when an input clock changes between lower and higher periods (2026-09-08),
2. 12712553 - GAIN CALIBRATION OF DIGITAL-TO-TIME CONVERTER (DTC) USED IN FRACTIONAL FREQUENCY DIVIDERS (2026-08-18),
3. 12603657 - Reducing non-linearity in a digital-to-time converter (DTC) due to unequal successive input codes specifying respective delays (2026-04-14),
4. 12261609 - Inter-PLL communication in a multi-PLL environment (2025-03-25),
5. 12249996 - Counter design for a time-to-digital converter (TDC) (2025-03-11),
6. 12149255 - Generating divided signals from phase-locked loop (PLL) output when reference clock is unavailable (2024-11-19),
7. 12026028 - Preventing reverse-current flow when an integrated circuit operates using power supplies of different magnitudes (2024-07-02),
8. 11967965 - Generating divided signals from phase-locked loop (PLL) output when reference clock is unavailable (2024-04-23),
9. 11923864 - Fast switching of output frequency of a phase locked loop (PLL) (2024-03-05),
10. 11799487 - Fractional sampling-rate converter to generate output samples at a higher rate from input samples (2023-10-24),
11. 11736110 - Time-to-digital converter (TDC) to operate with input clock signals with jitter (2023-08-22),
12. 11711087 - Reducing noise contribution in compensating for unequal successive time periods of a reference clock in a fractional-N phase locked loop (2023-07-25),
13. 11658667 - Reduction of noise in output clock due to unequal successive time periods of a reference clock in a fractional-N phase locked loop (2023-05-23),
14. 11592786 - Time-to-digital converter (TDC) measuring phase difference between periodic inputs (2023-02-28),
15. 11588489 - Obtaining lock in a phase-locked loop (PLL) upon being out of phase-lock (2023-02-21),

Title: Innovations of Raja Prabhu J: A Pioneer in Semiconductor Technology

Introduction

Raja Prabhu J is a notable inventor based in Bengaluru, India, recognized for his significant contributions to the field of semiconductor technology. With a remarkable portfolio of 16 patents, he has made strides in developing advanced electronic systems that enhance performance and efficiency.

Latest Patents

Among his latest innovations is the patent for "Inter-PLL communication in a multi-PLL environment." This invention involves an electronic block that incorporates multiple independent Phase-Locked Loops (PLLs) and a switch matrix. Each PLL features an input and output path, allowing the switch matrix to connect signals from one PLL to another. This design enables the generation of a combined frequency-correction signal, which is crucial for producing a stable output clock. Additionally, Raja has developed a patent for a "Counter design for a time-to-digital converter (TDC)." This TDC includes a counter that generates a sequence of counts based on clock signal transitions, utilizing both asynchronous and synchronous circuits to enhance accuracy.

Career Highlights

Raja Prabhu J has worked with prominent companies in the semiconductor industry, including Shaoxing Yuanfang Semiconductor Co., Ltd. and Aura Semiconductor Pvt. Ltd. His experience in these organizations has allowed him to refine his skills and contribute to groundbreaking projects in electronic design.

Collaborations

Throughout his career, Raja

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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