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Bengaluru, India

Raja Prabhu J

USPTO Granted Patents = 16 (Patent Applications = 7)

EPO Patents = 1 (Patent Applications = 1)

Average Co-Inventor Count = 5.1

ph-index = 2

Forward Citations = 13(Granted Patents)

Company Filing History:

Shaoxing Yuanfang Semiconductor Co., Ltd.

Aura Semiconductor Pvt. Ltd

Ningbo Aura Semiconductor Co., Limited

Years Active: 2017-2025

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16 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 12261609 - Inter-PLL communication in a multi-PLL environment (2025-03-25),

2. 12249996 - Counter design for a time-to-digital converter (TDC) (2025-03-11),

3. 12149255 - Generating divided signals from phase-locked loop (PLL) output when reference clock is unavailable (2024-11-19),

4. 12026028 - Preventing reverse-current flow when an integrated circuit operates using power supplies of different magnitudes (2024-07-02),

5. 11967965 - Generating divided signals from phase-locked loop (PLL) output when reference clock is unavailable (2024-04-23),

6. 11923864 - Fast switching of output frequency of a phase locked loop (PLL) (2024-03-05),

7. 11799487 - Fractional sampling-rate converter to generate output samples at a higher rate from input samples (2023-10-24),

8. 11736110 - Time-to-digital converter (TDC) to operate with input clock signals with jitter (2023-08-22),

9. 11711087 - Reducing noise contribution in compensating for unequal successive time periods of a reference clock in a fractional-N phase locked loop (2023-07-25),

10. 11658667 - Reduction of noise in output clock due to unequal successive time periods of a reference clock in a fractional-N phase locked loop (2023-05-23),

11. 11592786 - Time-to-digital converter (TDC) measuring phase difference between periodic inputs (2023-02-28),

12. 11588489 - Obtaining lock in a phase-locked loop (PLL) upon being out of phase-lock (2023-02-21),

13. 10892765 - Relocking a phase locked loop upon cycle slips between input and feedback clocks (2021-01-12),

14. 10700669 - Avoiding very low duty cycles in a divided clock generated by a frequency divider (2020-06-30),

15. 10514720 - Hitless switching when generating an output clock derived from multiple redundant input clocks (2019-12-24),

Title: Innovations of Raja Prabhu J: A Pioneer in Semiconductor Technology

Introduction

Raja Prabhu J is a notable inventor based in Bengaluru, India, recognized for his significant contributions to the field of semiconductor technology. With a remarkable portfolio of 16 patents, he has made strides in developing advanced electronic systems that enhance performance and efficiency.

Latest Patents

Among his latest innovations is the patent for "Inter-PLL communication in a multi-PLL environment." This invention involves an electronic block that incorporates multiple independent Phase-Locked Loops (PLLs) and a switch matrix. Each PLL features an input and output path, allowing the switch matrix to connect signals from one PLL to another. This design enables the generation of a combined frequency-correction signal, which is crucial for producing a stable output clock. Additionally, Raja has developed a patent for a "Counter design for a time-to-digital converter (TDC)." This TDC includes a counter that generates a sequence of counts based on clock signal transitions, utilizing both asynchronous and synchronous circuits to enhance accuracy.

Career Highlights

Raja Prabhu J has worked with prominent companies in the semiconductor industry, including Shaoxing Yuanfang Semiconductor Co., Ltd. and Aura Semiconductor Pvt. Ltd. His experience in these organizations has allowed him to refine his skills and contribute to groundbreaking projects in electronic design.

Collaborations

Throughout his career, Raja

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