Shaoxing Yuanfang Semiconductor Co., Ltd.

Aura Semiconductor Pvt. Ltd

Ningbo Aura Semiconductor Co., Limited

St-ericsson India Pvt. Ltd.

Oct Circuit Technologies International Limited

Raja Prabhu J

Ankit Seedher

Srinath Sridharan

Debasish Behera

Sandeep Sasi

Rakesh Kumar Gupta

Purva Choudhary

Jeevabharathi G

Augusto Marques

Nandakishore Palla

Manikanta Sakalabhaktula

Nitesh Naidu

Shivam Agrawal

Girisha Angadi Basavaraja

Sudarshan Varadarajan

Akash Gupta

Chandrashekar Bg

Harshavardhan Reddy

Bhupendra Sharma

Akash Kumar Gupta

Nigesh Baladhandapani

Sriharsha Vasadi

Chandrashekar B G

Kulbhushan Thakur

Venkata Krishna Mohan Panchireddi

Anurag Pulincherry

Shuvadeep Mitra

Chandrasekhar Bg

Nandini Ganig Bs

Sharanaprasad Melkundi

Shyam Somayajula S

An electronic block includes multiple independent Phase-Locked Loops (PLLs) and a switch matrix. Each PLL has an input path and an output path. The switch matrix is operable to concurrently connect a respective signal on the output path of each PLL to the input path of another PLL. In an embodiment, each of the respective signals on the output paths is a corresponding frequency-correction signal generated by a low-pass filter (LPF) in the corresponding PLL. In an embodiment, each PLL includes a frequency-correction signal combiner to combine the frequency-correction signals received from any of the other PLLs with its own frequency-correction signal to form a combined frequency-correction signal. The combined frequency-correction signal is provided to a controlled oscillator in the PLL to generate an output clock of the PLL based on the combined frequency-correction signal. The frequency-correction signals may be analog or digital signals.

Inter-PLL communication in a multi-PLL environment

A time-to-digital converter (TDC) includes a counter and a digital core. The counter is designed to generate a sequence of counts representing a number of transitions of interest of a first clock signal. The counter includes an asynchronous circuit and a synchronous circuit to respectively generate a first set of bits and a second set of bits of each of the sequence of numbers. The digital core is designed to process a pair of counts of the sequence.

Counter design for a time-to-digital converter (TDC)

Clock generation circuit generating multiple divided signals satisfying respective desired offsets. A phase locked loop (PLL) is used to generate a PLL output having a frequency which is a desired multiple of that of a reference clock. The circuit divides the PLL output by a corresponding divisor to generate a corresponding divided signal, wherein each divided signal is offset from a common reference by at least an associated desired time offset. The common reference is timed with respect to the reference clock when the reference clock is available and with respect to a time reference signal otherwise. This arrangement is extended to use the internal time reference signal even for the cases where the reference clock is present by blocking the reference clock while the output systems across PLLs are aligned using the internal time reference signal to ensure desired offsets across different PLLs with a small uncertainty.

Generating divided signals from phase-locked loop (PLL) output when reference clock is unavailable

An integrated circuit (IC) includes input/output (I/O) ports, each operating using one of a pair of unequal power supplies during normal operation of the IC. A lower supply of the pair of unequal power supplies is required to be used as the power supply for the I/O port when a first input signal to the IC is received from an external source on a first I/O port of the I/O ports. The voltage range of the logic excursions of the first input signal is greater than the range from a magnitude of the lower supply to a constant reference potential. A regulation loop derives a derived lower supply having a magnitude equaling that of the lower supply from the higher supply of the pair of unequal power supplies, and applies the derived lower supply on a power supply node of the first I/O port.

Preventing reverse-current flow when an integrated circuit operates using power supplies of different magnitudes

A phase-locked loop (PLL) is implemented to have another (second) PLL in place of the controlled oscillator. When a known frequency change in the frequency of the output clock is desired, in addition to changing a configuration of the PLL (first PLL), the configuration of the second PLL is also changed to cause the frequency of the output clock to change quickly. In various embodiments, the configuration of the second PLL is changed by changing the divisor of the feedback divider of the second PLL, the divisor in a pre-scaler in the second PLL, the control voltage of a VCO used in the second PLL, and any other point of user control in the second PLL.

Fast switching of output frequency of a phase locked loop (PLL)

A fractional sampling-rate converter includes a first-in first-out (FIFO) buffer, a write logic, a read logic and a fractional interpolator. The write logic is designed to write input data samples into the FIFO at a first rate. The fractional interpolator is coupled to receive the input data samples from the FIFO and is designed to generate corresponding interpolated data samples as an output of the fractional sampling-rate converter at a second rate. The read logic is designed to cause input data samples in the FIFO buffer to be transferred to the fractional interpolator. A ratio of the second rate and the first rate is a fractional number greater than one.

Fractional sampling-rate converter to generate output samples at a higher rate from input samples

A time-to-digital converter (TDC) provided according to an aspect of the present disclosure identifies existence of jitter in either one of two periodic signals received as inputs. In an embodiment, jitter is detected by examining a first sequence of counts and a second sequence of counts respectively for a first periodic signal and a second periodic signal received as input signals, with the first sequence of counts representing respective time instances on a time scale at which a first sequence of edges with a first direction of the first periodic signal occur, and the second sequence of counts representing respective time instances on the time scale at which a second sequence of edges with the first direction of the second periodic signal occur.

Time-to-digital converter (TDC) to operate with input clock signals with jitter

Enhancing the accuracy in compensating errors caused by a reference signal with unequal successive periods in a fractional-N phase locked loop (PLL). A compensation block generates a compensation factor, and is implemented based on a correction block and a filter. The correction block generates a correction signal containing a first frequency correction factor and a second frequency correction factor for a first period and a second period constituting each pair of successive periods, with the correction signal also containing a noise component at direct current (DC). The filter operates to remove the noise component at DC from the correction signal to generate a compensation factor containing the first frequency correction factor and the second frequency correction factor. The compensation factor thus generated may be provided as an input to a division factor generator of a frequency divider block of the PLL, potentially resulting in zero error frequency synthesis.

Reducing noise contribution in compensating for unequal successive time periods of a reference clock in a fractional-N phase locked loop

A division factor generator of a feedback divider block in a fractional-N phase locked loop (PLL). The division factor generator is enabled to operate with larger values of division factors without increased complexity of an internal modulator core implemented, for example, as a delta-sigma modulator (DSM) having a signal transfer function (STF), wherein the STF always generates only an integer value as an output in response to an integer value received as input.

Reduction of noise in output clock due to unequal successive time periods of a reference clock in a fractional-N phase locked loop

A time-to-digital converter (TDC) includes a count logic and a digital core. The count logic generates a first sequence of counts representing a first sequence of edges of a first periodic signal, and a second sequence of counts representing a second sequence of edges of a second periodic signal. The digital core generates a sequence of outputs representing the phase differences between the first periodic signal and the second periodic signal from the first sequence of counts and the second sequence of counts. Each output is generated from a pair of successive edges of the first direction of one of the periodic signals and an individual one of the other periodic signal occurring between the pair, and the output is set equal to the minimum of difference of the individual one with the first value of the pair and the individual one with the second value of the pair.

Time-to-digital converter (TDC) measuring phase difference between periodic inputs

A phase-locked loop (PLL) provided according to an aspect of the present disclosure includes a phase detector, a low-pass filter, an oscillator, an output block and a phase locking block. The oscillator generates an intermediate clock and the output block generates each of successive cycles of a feedback clock on counting a pre-determined number of cycles of the intermediate clock. The phase locking block, upon detecting the PLL being out of phase-lock, controls the operation of the output block to obtain phase-lock in the PLL within two cycles of the input clock from the time of detection of the PLL being out of phase-lock.

Obtaining lock in a phase-locked loop (PLL) upon being out of phase-lock

A phase locked loop (PLL) includes a phase detector, a first low-pass filter, an oscillator, a feedback divider and a cycle slip detector. The cycle slip detector is operable to detect at a first time instance, a cycle slip between an input clock and a feedback clock of the PLL. Upon detection of the cycle slip, the cycle slip detector is operable to increase a loop BW of the PLL. As a result, faster relocking of the PLL is achieved upon occurrence of an abrupt and large frequency difference between the input clock and the feedback clock.

Relocking a phase locked loop upon cycle slips between input and feedback clocks

A frequency divider includes a set of frequency-dividing units coupled in series in a sequential order, with the sequence of frequency-dividing units including a lowest unit and a highest unit, with the remaining units being disposed in series between the lowest unit and the highest unit. The lowest unit is coupled to receive an input clock whose frequency is to be divided and provided as an output clock. Each frequency-dividing unit in the set is coupled to receive a corresponding first clock as an input and is operable to generate a corresponding second clock as an output. The frequency divider includes a logic block to generate a first set of edges of the output clock synchronous with the input clock. The logic block is designed to generate a second set of edges of the output clock synchronous with the output clock of a highest operative frequency-dividing unit in the set.

Avoiding very low duty cycles in a divided clock generated by a frequency divider

A phase locked loop (PLL) includes a multiplexer (MUX), a phase detector, a filter block, an oscillator, a frequency divider, and a clock switch controller, and achieves hitless switching between a primary clock and a redundant clock. The clock switch controller, upon detecting a condition requiring switching from the primary clock to the redundant clock, is operable to restart the feedback divider synchronously with respect to the redundant clock, and derive the output of the PLL from the redundant clock. The PLL further includes a delay block to process delayed phase error signals generated by the phase detector. The PLL performs hitless clock switching in the event of input clock loss or in response to a command to switch input clocks. The PLL further includes circuitry for estimating and cancelling residual phase errors.

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Bengaluru, India

Raja Prabhu J