Gainesville, FL, United States of America

Pravin Dasharth Gaikwad

This inventor holds 4 USPTO granted patents and 1 published patent application. Top assignees: University of Florida Research Foundation Inc., Intel Corporation. Active years: 2022-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Pravin Dasharth Gaikwad. Retrieved from https://idiyas.com/inventor/pravin-dasharth-gaikwad

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 4 

% Patents Active = 75.0

Average Co-Inventor Count = 5.6

ph-index = 1

Forward Citations = 1(Granted Patents)


Company Filing History:


Years Active: 2022-2026

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4 patents (USPTO):Explore Patents

Title: Innovations by Pravin Dasharth Gaikwad

Introduction

Pravin Dasharth Gaikwad is an accomplished inventor based in Gainesville, Florida. He has made significant contributions to the field of digital design security, holding two patents that showcase his innovative approach to enhancing the integrity of electronic systems.

Latest Patents

One of his latest patents is titled "Invisible scan architecture for secure testing of digital designs." This invention provides a scan-based architecture for register-transfer-level (RTL) or gate-level designs, improving the security of scan chain-based design-for-testability (DFT) structures. The architecture includes invisible scan chains that are concealed to prevent attackers from easily identifying or exploiting them, thereby protecting internal secure information. The invisible scan chains can be dynamically configured, allowing for different scan paths across various designs, chips, or testing operations. Additionally, the invention employs key-based obfuscation, enhancing design security against unauthorized use and increasing confidentiality.

Another notable patent is "Systems and methods for machine intelligence based malicious design alteration insertion." This patent outlines methods and apparatus for generating an insertion netlist for a target circuit, which is configured to insert a malicious design alteration based on design identifying reference trigger nets. The process involves extracting features for each net in the circuit's netlist and generating a set of reference trigger features. A net is selected based on the similarity between its features and the reference trigger features, resulting in an insertion netlist that includes the circuit with the malicious alteration.

Career Highlights

Pravin Gaikwad is affiliated with the University of Florida Research Foundation, Incorporated, where he continues to advance his research and innovations in digital design security. His work has garnered attention for its potential to significantly enhance the security of electronic systems.

Collaborations

He has collaborated with notable colleagues, including Swarup Bhunia and Jonathan William Cruz, contributing to a dynamic research environment that fosters innovation and development in the field.

Conclusion

Pravin Dasharth Gaikwad's contributions to digital design security through his innovative patents reflect his commitment to advancing technology. His work not only enhances the security of electronic systems but also sets a foundation for future innovations in the field.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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