The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2022

Filed:

Sep. 29, 2020
Applicant:

University of Florida Research Foundation, Incorporated, Gainesville, FL (US);

Inventors:

Swarup Bhunia, Gainesville, FL (US);

Prabuddha Chakraborty, Gainesville, FL (US);

Abhishek A. Nair, Gainesville, FL (US);

Tamzidul Hoque, Gainesville, FL (US);

Jonathan W. Cruz, Gainesville, FL (US);

Naren Masna, Gainesville, FL (US);

Pravin Gaikwad, Gainesville, FL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/323 (2020.01); G06F 30/398 (2020.01); G06F 21/55 (2013.01); G06N 20/00 (2019.01);
U.S. Cl.
CPC ...
G06F 30/323 (2020.01); G06F 21/55 (2013.01); G06F 30/398 (2020.01); G06N 20/00 (2019.01);
Abstract

Embodiments of the present disclosure provide methods, apparatus, and computer program products for generating an insertion netlist for a target circuit configured for inserting a malicious design alteration into the circuit based on a design identifying reference trigger nets. Features are extracted for each net identified in a netlist for the circuit. A set of reference trigger features is generated for each of the reference trigger nets. A net is selected from the netlist for each set of reference trigger features based on a similarity between the features of the net and the set of reference trigger features. The insertion netlist is generated that includes the circuit with the malicious design alteration inserted at each of the selected nets.


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