Company Filing History:
Years Active: 2019
Title: **Innovator Po-Cheng Pan: Advancements in Integrated Circuit Layout**
Introduction
Po-Cheng Pan, an accomplished inventor based in Hsinchu, Taiwan, has made significant contributions to the field of integrated circuit (IC) design. With two patents to his name, his innovative methods focus on enhancing layout generation and routing preservation, pivotal aspects of IC technology.
Latest Patents
Po-Cheng Pan's latest patents reflect his expertise in optimizing layout generation for integrated circuits. One notable patent is for a **Method for Layout Generation with Constrained Hypergraph Partitioning**. This method involves accessing schematic design data, generating a hypergraph from that design, and applying constraints to create weighted edges for effective partitioning. The result is a multilevel grouping that leads to an improved IC layout, which is then verified for fabrication.
Another groundbreaking patent is titled **Efficient Analog Layout Prototyping by Layout Reuse with Routing Preservation**. This computer-implemented method allows the decomposition of geometric relationships between modules in a source layout. By doing so, it enables the strategic placement of routing paths in solution layouts without relying solely on scaling from the original design, thus enhancing the efficiency of analog layouts.
Career Highlights
Throughout his career, Po-Cheng Pan has collaborated with prestigious companies such as Taiwan Semiconductor Manufacturing Company Limited and Synopsys, Inc. These affiliations underscore his impact within the industry and highlight his role in advancing semiconductor technologies.
Collaborations
Po-Cheng Pan has worked alongside notable colleagues including Hung-Ming Chen and Tsun-Yu Yang. Their collective expertise and collaborative efforts have contributed to innovative solutions in IC design and layout optimization.
Conclusion
With his two patents, Po-Cheng Pan stands out as a significant figure in integrated circuit innovation. His contributions not only enhance the efficiency of layout generation but also improve the overall process of IC fabrication, making a lasting impact on semiconductor technology.
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