Taiwan Semiconductor Manufacturing Comp. Ltd.

Synopsys, Inc.

Po-Cheng Pan

Hung-Ming Chen

Jui-Feng Kuan

Hsien-Hsin Sean Lee

Wei-Yi Hu

Tung-Chieh Chen

Tsun-Yu Yang

Hung-Wen Huang

Abhishek Patyal

Ching-Yu Chin

A layout-generation method for an IC is provided. The layout-generation method includes accessing data of a schematic design of the IC; generating a hypergraph from the schematic design; transforming a plurality of constraints into a plurality of weighted edges in the hypergraph; continuing partitioning the hypergraph by the weighted edges until a plurality of multilevel groups are obtained to generate a layout; and verifying the layout to fabricate the IC.

Method for layout generation with constrained hypergraph partitioning

A computer implemented method for routing preservation is presented. The method includes decomposing, using the computer, a geometric relationship between a first module, a second module, and a routing path of a source layout, when the computer is invoked to route the solution path. The method further includes disposing, using the computer, the routing path in a solution layout in accordance with the geometric relationship. The solution layout is not defined by a scaling of the source layout.

Efficient analog layout prototyping by layout reuse with routing preservation

Growing community of inventors

Hsinchu, Taiwan

Po-Cheng Pan