The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 17, 2019
Filed:
Jan. 24, 2017
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Tsun-Yu Yang, Changhua, TW;
Wei-Yi Hu, Zhubei, TW;
Jui-Feng Kuan, Zhubei, TW;
Hsien-Hsin Sean Lee, Duluth, GA (US);
Po-Cheng Pan, Hsinchu, TW;
Hung-Wen Huang, Taoyuan, TW;
Hung-Ming Chen, Zhubei, TW;
Abhishek Patyal, Hsinchu, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;
Abstract
A layout-generation method for an IC is provided. The layout-generation method includes accessing data of a schematic design of the IC; generating a hypergraph from the schematic design; transforming a plurality of constraints into a plurality of weighted edges in the hypergraph; continuing partitioning the hypergraph by the weighted edges until a plurality of multilevel groups are obtained to generate a layout; and verifying the layout to fabricate the IC.