This inventor holds 1 USPTO granted patent. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2019.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
Company Filing History:
Years Active: 2019
Title: Abhishek Patyal: Innovator in Integrated Circuit Design
Introduction
Abhishek Patyal is a notable inventor based in Hsinchu, Taiwan. He has made significant contributions to the field of integrated circuit (IC) design, particularly through his innovative patent.
Latest Patents
Abhishek holds a patent titled "Method for layout generation with constrained hypergraph partitioning." This patent describes a layout-generation method for an IC that includes accessing data from a schematic design, generating a hypergraph, transforming constraints into weighted edges, partitioning the hypergraph, and verifying the layout for fabrication.
Career Highlights
Abhishek is currently employed at Taiwan Semiconductor Manufacturing Company Limited, a leading firm in the semiconductor industry. His work focuses on enhancing the efficiency and effectiveness of IC layout generation.
Collaborations
Abhishek collaborates with talented coworkers, including Tsun-Yu Yang and Wei-Yi Hu, who contribute to his innovative projects and research.
Conclusion
Abhishek Patyal's contributions to IC design through his patented methods highlight his role as an influential inventor in the technology sector. His work continues to impact the field positively.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile