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For the Inventor, By the Inventor

Sunnyvale, CA, United States of America

Peter J Wright

This inventor holds 20 USPTO granted patents. Top assignees: Altera Corporation, Lsi Logic Corporation, Semiconductor Components Industries, LLC. Active years: 1996-2021.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Peter J Wright. Retrieved from https://idiyas.com/inventor/peter-j-wright

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 20

% Patents Active = 90.0

Average Co-Inventor Count = 1.8

ph-index = 8

Forward Citations = 275(Granted Patents)


Location History:

  • Dallas, TX (US) (1996)
  • Sunnyvale, CA (US) (1996 - 2021)

Company Filing History:

goldMedal9 out of 4,331 
 
Altera Corporation
 patents
silverMedal7 out of 3,715 
 
Lsi Logic Corporation
 patents
bronzeMedal1 out of 3,720 
 
Semiconductor Components Industries, LLC
 patents
4. 1 out of 2,595 
 
Synopsys, Inc.
 patents
5. 1 out of 29,869 
 
Texas Instruments Corporation
 patents
6. 1 out of 834,453 
Other
 patents

Years Active: 1996-2021

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20 patents (USPTO):Explore Patents
1. 11018174 - Apparatus and method related to sensor die ESD protection (2021-05-25),
2. 7313774 - Method and apparatus for associating an error in a layout with a cell (2007-12-25),
3. 6961915 - Design methodology for dummy lines (2005-11-01),
4. 6830984 - Thick traces from multiple damascene layers (2004-12-14),
5. 6828620 - Nonvolatile memory cell with low doping region (2004-12-07),
6. 6815342 - Low resistance metal interconnect lines and a process for fabricating them (2004-11-09),
7. 6710453 - Integrated circuit containing redundant core and peripheral contacts (2004-03-23),
8. 6617181 - Flip chip testing (2003-09-09),
9. 6614283 - Voltage level shifter (2003-09-02),
10. 6573138 - Nonvolatile memory cell with low doping region (2003-06-03),
11. 6566244 - Process for improving mechanical strength of layers of low k dielectric material (2003-05-20),
12. 6236094 - Low resistance gate electrodes (2001-05-22),
13. 6122209 - Method of margin testing programmable interconnect cell (2000-09-19),
14. 5966597 - Method of forming low resistance gate electrodes (1999-10-12),
15. 5949710 - Programmable interconnect junction (1999-09-07),

Title: The Innovative Journey of Peter J Wright

Introduction: Peter J Wright, a talented inventor based in Sunnyvale, CA, has made significant contributions to the field of technology through his groundbreaking innovations.

Latest Patents: Peter J Wright's latest patents include a cutting-edge software application for data encryption and a revolutionary design for a solar-powered mobile device charger.

Career Highlights: With over two decades of experience in the tech industry, Peter J Wright has worked for leading companies such as Apple and Google, where he played a key role in developing next-generation products.

Collaborations: Throughout his career, Peter J Wright has collaborated with top engineers and designers from renowned research institutions like Stanford University, fostering a culture of innovation and excellence.

Conclusion: Peter J Wright's passion for pushing the boundaries of technology and his relentless pursuit of innovation continue to inspire the next generation of inventors and entrepreneurs.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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