Altera Corporation

Lsi Logic Corporation

Other

Texas Instruments Corporation

Semiconductor Components Industries, LLC

Synopsys, Inc.

Peter J Wright

Rakesh H Patel

Raminda U Madurawe

John E Turner

James D Sansbury

Christopher J Pass

Venkatesh P Gopinath

Payman Zarkesh-Ha

Charles E May

Richard Thomas Schultz

Todd A Randazzo

Chuan-Cheng Cheng

William Loh

Siang Ping Kwok

Benjamin Mbouombouo

Hong Ying

Sethuraman Lakshminarayanan

Minghui Fan

Techniques of drawing ESD current away from an image sensor device of a CMOS image sensor die include using a light shield configured to block light from an image sensor device. The light shield may be used to draw the ESD current away when it has an electrical connection to an ESD ground bus and/or to a bond pad of the CMOS image sensor die. Advantageously, the light shield has a low resistance due to its large surface area. Accordingly, parallel connections to the bond pads and/or ESD bus have a resistance close to the low resistance of the light shield without altering the size of the die.

Apparatus and method related to sensor die ESD protection

One embodiment of the present invention provides a system that associates an error in a layout with a cell. During operation, the system receives a layout which is designed to create a target feature with an intended shape. Next, the system determines an error in a critical dimension of the target feature. The system then identifies a cell in the layout based on the error's location in the layout, thereby associating the error with the cell. Note that associating errors with cells allows the errors to be summarized based on the associated cells, which can reduce the amount of time required to identify and fix the errors.

Method and apparatus for associating an error in a layout with a cell

A method and system for designing a dummy grid in an open area of a circuit adjacent to at least one metal line comprising the circuits is disclosed. The method and system include patterning dummy lines in the dummy grid adjacent to metal signal lines, and patterning non-floating dummy lines in the dummy grid adjacent to metal power lines. The method and system further include varying sizes and spacing of the dummy lines in the respective columns of the dummy grid based on the distance between each column and the adjacent metal line, to achieve a balance between planarization and performance.

Design methodology for dummy lines

Multiple damascene layers in integrated circuits can form several advantageous designs or components that may lower cost or increase performance of certain designs. In embodiments for power bus signals, multiple damascene layers may be used to form traces with increased power capacity and lower cost. In other embodiments, multiple damascene layers may be used to form components such as capacitors and inductors with increased performance.

Thick traces from multiple damascene layers

A technique of fabricating a nonvolatile device includes forming a low doping region to aid in the reduction of substrate hot electrons. The nonvolatile device may be a floating gate device, such as a Flash, EEPROM, or EPROM memory cell. The low doping region has a lower doping concentration than that of the substrate. By reducing substrate hot electrons, this improves the reliability and longevity of the nonvolatile device.

Nonvolatile memory cell with low doping region

Low resistance interconnect lines and methods for fabricating them are described herein. IC fabrication processes are used to create interconnect lines of Al and Cu layers. The Cu layer is thinner than in the known art, but in combination with the Al layer, the aggregate Cu/Al resistance is lowered to a point where it is comparable to that of a very thick Cu layer, without the additional cost and yield problems caused by using a thicker Cu deposition. Fuses for memory repair can also be fabricated using the methods taught by the present invention with only small variations in the process.

Low resistance metal interconnect lines and a process for fabricating them

An integrated circuit having circuit structures, including at least one of logic elements and memory elements. A core is disposed at an interior portion of the integrated circuit. The core contains core power contacts and core ground contacts for providing electrical power to the circuit structures during functional operation of the integrated circuit. A peripheral is disposed at an edge portion of the integrated circuit. The peripheral contains signal contacts for sending and receiving electrical signals between the circuit structures and external circuitry. The peripheral also has peripheral power contacts and peripheral ground contacts for providing electrical power to the circuit structures during testing of the integrated circuit. The peripheral power contacts are redundant to at least some of the core power contacts, and the peripheral ground contacts are redundant to at least some of the core power contacts.

Integrated circuit containing redundant core and peripheral contacts

Flip chip testing

In an integrated circuit, a voltage level shifter transitions an input signal at a first voltage level to an output signal at a second voltage level. The voltage level shifter generally includes switching elements, such as transistors, that control switching the output signal between logical zero and logical one values. The switching elements have a maximum voltage below which they can operate. The maximum voltage is less than the second voltage level. The voltage across the switching elements is limited to less than the maximum voltage.

Voltage level shifter

A process for selectively reinforcing portions of a low k dielectric material which comprises first forming a low k dielectric layer, then forming openings in the low k layer in portions of the low k layer needing reinforcement, and then filling the openings with reinforcing material, preferably reinforcing material having a higher Young's modulus of elasticity than the low k dielectric material. Such selective reinforcement of certain portions of low k dielectric material may comprise selectively reinforcing the low k dielectric material beneath the bonding pads, with reinforcing material. The low k dielectric material may be reinforced by openings in the low k dielectric material formed beneath portions of the low k dielectric layer where a capping layer will be formed over the low k dielectric material. Subsequent formation of the capping layer will simultaneously fill the openings with capping material, which may then also function as reinforcement material in the openings.

Process for improving mechanical strength of layers of low k dielectric material

Provided is a transistor device, and a process for fabricating such a device, in which a top portion of a polysilicon gate electrode is removed and replaced by a low resistance metal material using a damascene process. Gate electrodes in accordance with the present invention provide improved conductivity over conventional polysilicon and silicide-capped polysilicon gate electrodes, due to the low resistivity of the metal, but do not have the drawbacks associated with the complete removal and replacement of polysilicon with a metal.

Low resistance gate electrodes

A static, nonvolatile, and reprogrammable programmable interconnect junction cell for implementing programmable interconnect in an integrated circuit. The programmable interconnect junction (600) is programmably configured to couple or decouple a first interconnect line (210) and a second interconnect line (220). The configured state of the programmable interconnect junction is detected directly, and memory cell detection circuitry such as sense amplifiers are not needed during normal operation. Full-rail voltages may be passed from the first interconnect line and the second interconnect line.

Growing community of inventors

Sunnyvale, CA, United States of America

Peter J Wright