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For the Inventor, By the Inventor

Bengaluru, India

Pattabhiraman K

This inventor holds 54 USPTO granted patents and 11 published patent applications and 11 EPO patents, primarily in Graphics Processing. Top assignee: Intel Corporation. Active years: 2016-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Pattabhiraman K. Retrieved from https://idiyas.com/inventor/pattabhiraman-k

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 54 

% Patents Active = 100.0

 

Average Co-Inventor Count = 9.0

ph-index = 6

Forward Citations = 149(Granted Patents)


Location History:

  • Bangalore KA, IN (2020)
  • Bengaluru, IN (2016 - 2024)

Company Filing History:

goldMedal54 out of 56,365 
 
Intel Corporation
 patents

Years Active: 2016-2026

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Areas of Expertise:
Graphics Virtualization
Cache Optimization
Memory Management
Low Power Inference
Multi-GPU Configuration
Augmented Reality
Dynamic Memory Reconfiguration
Latency Measurement
Quality of Service
Data Compression
Virtual Environments
Operation Scheduling
54 patents (USPTO):Explore Patents
1. 12754876 - Cache structure and utilization (2026-10-06),
2. 12737318 - Cache structure and utilization (2026-09-15),
3. 12737317 - Systems and methods for updating memory side caches in a multi-GPU configuration (2026-09-15),
4. 12730759 - Systems and methods for cache optimization (2026-09-08),
5. 12608871 - Apparatus and method for efficient graphics virtualization (2026-04-21),
6. 12579072 - Graphics processor register file including a low energy portion and a high capacity portion (2026-03-17),
7. 12561276 - Systems and methods for updating memory side caches in a multi-GPU configuration (2026-02-24),
8. 12461781 - Low power inference engine pipeline in a graphics processing unit (2025-11-04),
9. 12386779 - Dynamic memory reconfiguration (2025-08-12),
10. 12367063 - Technology to measure latency in hardware with fine-grained transactional filtration (2025-07-22),
11. 12210477 - Systems and methods for improving cache efficiency and utilization (2025-01-28),
12. 12182035 - Systems and methods for cache optimization (2024-12-31),
13. 12153541 - Cache structure and utilization (2024-11-26),
14. 12124383 - Systems and methods for cache optimization (2024-10-22),
15. 12079155 - Graphics processor operation scheduling for deterministic latency (2024-09-03),

Title: Inventor Pattabhiraman K: Revolutionizing Technology in Bengaluru

Introduction: Pattabhiraman K is a visionary inventor based in Bengaluru, India, known for his groundbreaking contributions to the field of technology.

Latest Patents: Pattabhiraman K holds several patents in the areas of artificial intelligence, machine learning, and robotics, showcasing his innovative approach to solving complex problems.

Career Highlights: With a career spanning over two decades, Pattabhiraman K has worked with leading tech companies, research institutions, and universities, honing his skills and expertise in cutting-edge technologies.

Collaborations: Throughout his career, Pattabhiraman K has collaborated with top researchers, engineers, and scientists from around the world, fostering a culture of innovation and creativity in his projects.

Conclusion: Inventor Pattabhiraman K continues to push the boundaries of technology, inspiring the next generation of inventors and leaving a lasting impact on the industry.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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