Intel Corporation

Pattabhiraman K

Abhishek R Appu

Altug Koker

Joydeep Ray

Balaji Vembu

Vasanth Ranganathan

Elmoustapha Ould-Ahmed-Vall

Prasoonkumar Surti

Lakshminarayanan Striramassarma

Kamal Sinha

Subramaniam M Maiyuran

David M Puffer

Niranjan L Cooray

Varghese George

Ankur N Shah

Aravindh V Anantaraman

Valentin Andrei

James M Holland

Radhakrishnan Venkataraman

Sayan Lahiri

Kiran Chand Veernapu

Scott R Janus

Chandrasekaran Sakthivel

Ben J Ashbaugh

Brent E Insko

Sungye Kim

Travis T Schluessler

Rajesh M Sankaran

Michael Apodaca

Kai Xiao

Kun Tian

Peter L Doyle

Deepak Shashidhar Vembar

Jeffery S Boles

Mike MacPherson

David J Cowperthwaite

Hema Chand Nalluri

Sameer Kp

Vivek Tiwari

Matthew B Callaway

Durgaprasad Bilagi

Satyeshwar Singh

Sanjeev S Jahagirdar

Murali Ramadoss

Adam T Lake

Linda L Hurd

Devan Burke

Abhishek Venkatesh

Daniel Pohl

Wenyin Fu

Josh B Mastronarde

Bhushan M Borole

Philip R Laws

Xinmin Tian

Saurabh Sharma

Eric J Hoekstra

Jayakrishna P S

Aditya Navale

Nicolas C Galoppo Von Borries

James A Valerio

Vikranth Vemulapalli

Jonathan D Pearce

Arthur Hunter, Jr

Pratik M Marolia

William B Sadler

Yoav Harel

Sanjay Kumar

Brandon L Fliflet

Marian Alin Petre

Guadalupe J Garcia

Shailesh Shah

Nikos Kaburlasos

Ravishankar Iyer

Eric C Samson

Jason Daniel Tanner

John H Feit

Selvakumar Panneer

Jacek Kwiatkowski

Nilesh K Jain

Carson Brownlee

Jefferson Amstutz

Vidhya Krishnan

Anirban Kundu

Joseph Koston

Saurabh Tangri

Michael F Cole

Sean Coleman

Atlug Koker

Santosh Tripathy

Ankita A Agarwal

Chien-Wei Li

Hema Chand Nallluri

One embodiment provides an apparatus comprising a graphics processor device including a first compute engine and a second compute engine, wherein the second compute engine includes a subset of the functionality provided by the first compute engine and a lower power consumption relative to the first compute engine.

Low power inference engine pipeline in a graphics processing unit

Embodiments described herein provide techniques to enable the dynamic reconfiguration of memory on a general-purpose graphics processing unit. One embodiment described herein enables dynamic reconfiguration of cache memory bank assignments based on hardware statistics. One embodiment enables for virtual memory address translation using mixed four kilobyte and sixty-four kilobyte pages within the same page table hierarchy and under the same page directory. One embodiment provides for a graphics processor and associated heterogenous processing system having near and far regions of the same level of a cache hierarchy.

Dynamic memory reconfiguration

Methods, systems and apparatuses may provide for technology that includes configuration registers to maintain state information, a filter coupled to the configuration registers, the filter to extract transactions of interest from a plurality of incoming transactions based on the state information, wherein the transactions of interest are extracted on a transaction-by-transaction basis, a first hardware path coupled to the filter, the first hardware path to generate a count of the transactions of interest on a cycle-by-cycle basis, a second hardware path coupled to the filter, the second hardware path to measure a total latency of the transactions of interest on the cycle-by-cycle basis, and an output interface coupled to the first hardware path and the second hardware path, the output interface to determine an average latency of the transactions of interest based on the count of the transactions of interest and the total latency of the transactions of interest.

Technology to measure latency in hardware with fine-grained transactional filtration

Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache coupled to the processing resources. The cache controller is configured to control cache priority by determining whether default settings or an instruction will control cache operations for the cache.

Systems and methods for improving cache efficiency and utilization

Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache memory that is coupled to the processing resources. The cache controller is configured to set an initial aging policy using an aging field based on age of cache lines within the cache memory and to determine whether a hint or an instruction to indicate a level of aging has been received.

Systems and methods for cache optimization

Embodiments are generally directed to cache structure and utilization. An embodiment of an apparatus includes one or more processors including a graphics processor; a memory for storage of data for processing by the one or more processors; and a cache to cache data from the memory; wherein the apparatus is to provide for dynamic overfetching of cache lines for the cache, including receiving a read request and accessing the cache for the requested data, and upon a miss in the cache, overfetching data from memory or a higher level cache in addition to fetching the requested data, wherein the overfetching of data is based at least in part on a current overfetch boundary, and provides for data is to be prefetched extending to the current overfetch boundary.

Cache structure and utilization

Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache memory that is coupled to the processing resources. The cache controller is configured to set an initial aging policy using an aging field based on age of cache lines within the cache memory and to determine whether a hint or an instruction to indicate a level of aging has been received. In one embodiment, the cache memory configured to be partitioned into multiple cache regions, wherein the multiple cache regions include a first cache region having a cache eviction policy with a configurable level of data persistence.

Embodiments described herein include software, firmware, and hardware that provides techniques to enable deterministic scheduling across multiple general-purpose graphics processing units. One embodiment provides a multi-GPU architecture with uniform latency. One embodiment provides techniques to distribute memory output based on memory chip thermals. One embodiment provides techniques to enable thermally aware workload scheduling. One embodiment provides techniques to enable end to end contracts for workload scheduling on multiple GPUs.

Graphics processor operation scheduling for deterministic latency

Systems and methods for cache utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache memory that is coupled to the processing resources. The cache controller is configured to set an initial aging policy using an aging field based on age of cache lines within the cache memory and to determine whether a hint or an instruction to indicate a level of aging has been received. In one embodiment, the cache memory configured to be partitioned into multiple cache regions, wherein the multiple cache regions include a first cache region having a cache eviction policy with a configurable level of data persistence.

One embodiment provides circuitry coupled with cache memory and a memory interface, the circuitry to compress compute data at multiple cache line granularity, and a processing resource coupled with the memory interface and the cache memory. The processing resource is configured to perform a general-purpose compute operation on compute data associated with multiple cache lines of the cache memory. The circuitry is configured to compress the compute data before a write of the compute data via the memory interface to the memory bus, in association with a read of the compute data associated with the multiple cache lines via the memory interface, decompress the compute data, and provide the decompressed compute data to the processing resource.

Sector cache for compression

Systems, apparatuses and methods may provide away to enhance an augmented reality (AR) and/or virtual reality (VR) user experience with environmental information captured from sensors located in one or more physical environments. More particularly, systems, apparatuses and methods may provide a way to track, by an eye tracker sensor, a gaze of a user, and capture, by the sensors, environmental information. The systems, apparatuses and methods may render feedback, by one or more feedback devices or display device, for a portion of the environment information based on the gaze of the user.

Sensory enhanced augmented reality and virtual reality device

An apparatus and method for dynamic provisioning, quality of service, and prioritization in a graphics processor. For example, one embodiment of an apparatus comprises a graphics processing unit (GPU) comprising a plurality of graphics processing resources; slice configuration hardware logic to logically subdivide the graphics processing resources into a plurality of slices; and slice allocation hardware logic to allocate a designated number of slices to each virtual machine (VM) of a plurality of VMs running in a virtualized execution environment, the slice allocation hardware logic to allocate different numbers of slices to different VMs based on graphics processing requirements and/or priorities of each of the VMs.

Apparatus and method for dynamic provisioning, quality of service, and prioritization in a graphics processor

An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.

Apparatus and method for memory management in a graphics processing environment

Growing community of inventors

Bengaluru, India

Pattabhiraman K