The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 24, 2026
Filed:
Mar. 14, 2020
Intel Corporation, Santa Clara, CA (US);
Altug Koker, El Dorado Hills, CA (US);
Joydeep Ray, Folsom, CA (US);
Aravindh Anantaraman, Folsom, CA (US);
Valentin Andrei, San Jose, CA (US);
Abhishek Appu, El Dorado Hills, CA (US);
Sean Coleman, Folsom, CA (US);
Nicolas Galoppo Von Borries, Portland, OR (US);
Varghese George, Folsom, CA (US);
Pattabhiraman K, Bangalore, IN;
Sungye Kim, Folsom, CA (US);
Mike Macpherson, Portland, OR (US);
Subramaniam Maiyuran, Gold River, CA (US);
Elmoustapha Ould-Ahmed-Vall, Chandler, AZ (US);
Vasanth Ranganathan, El Dorado Hills, CA (US);
James Valerio, North Plains, OR (US);
INTEL CORPORATION, Santa Clara, CA (US);
Abstract
Systems and methods for updating remote memory side caches in a multi-GPU configuration are disclosed herein. In one embodiment, a graphics processor for a multi-tile architecture includes a first graphics processing unit (GPU) having a first memory, a first memory side cache memory, a first communication fabric, and a first memory management unit (MMU). The graphics processor includes a second graphics processing unit (GPU) having a second memory, a second memory side cache memory, a second memory management unit (MMU), and a second communication fabric that is communicatively coupled to the first communication fabric. The first MMU is configured to control memory requests for the first memory, to update content in the first memory, to update content in the first memory side cache memory, and to determine whether to update the content in the second memory side cache memory.