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For the Inventor, By the Inventor

Noida, India

Paras Garg

This inventor holds 16 USPTO granted patents and 4 published patent applications and 1 EPO patent. Top assignees: Stmicroelectronics International N.v., Stmicroelectronics Pvt. Ltd., Stmicroelectronics (Crolles 2) Sas. Active years: 2007-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Paras Garg. Retrieved from https://idiyas.com/inventor/paras-garg

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 16 

% Patents Active = 68.8

 

Average Co-Inventor Count = 2.6

ph-index = 6

Forward Citations = 69(Granted Patents)


Location History:

  • Ghaziabad, IN (2007 - 2009)
  • Uttar Pradesh, IN (2010 - 2012)
  • Noida, IN (2008 - 2022)

Company Filing History:

goldMedal10 out of 1,256 
 
Stmicroelectronics International N.v.
 patents
silverMedal6 out of 207 
 
Stmicroelectronics Pvt. Ltd.
 patents
bronzeMedal1 out of 781 
 
Stmicroelectronics (Crolles 2) Sas
 patents
where one patent can have more than one assignee

Years Active: 2007-2026

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16 patents (USPTO):Explore Patents
1. 12665592 - Device and method for bulk induced pre-emphasis technique in current mode transmitter for high speed links (2026-06-23),
2. 12572495 - PVT compensated slow transition serial interface IO transmitter with reduced delay (2026-03-10),
3. 12506479 - High-voltage fault protection circuit (2025-12-23),
4. 12212318 - Low-voltage differential signaling (LVDS) transmitter circuit (2025-01-28),
5. 11223354 - Low current, wide range input common mode LVDS receiver devices and methods (2022-01-11),
6. 10530366 - Low voltage differential signaling fault detector (2020-01-07),
7. 9473135 - Driver circuit including driver transistors with controlled body biasing (2016-10-18),
8. 8981817 - Operating conditions compensation circuit (2015-03-17),
9. 8253437 - Reduction of signal skew (2012-08-28),
10. 8207754 - Architecture for efficient usage of IO (2012-06-26),
11. 7902885 - Compensated output buffer for improving slew control rate (2011-03-08),
12. 7768311 - Suppressing ringing in high speed CMOS output buffers driving transmission line load (2010-08-03),
13. 7495483 - Input buffer for CMOS integrated circuits (2009-02-24),
14. 7425849 - Low noise output buffer capable of operating at high speeds (2008-09-16),
15. 7368976 - Method and apparatus for providing compensation against temperature, process and supply voltage variation (2008-05-06),

Title: Inventor Paras Garg: Revolutionizing Technology in Noida

Introduction: Paras Garg is a visionary inventor based in Noida, India, known for his groundbreaking contributions to the field of technology.

Latest Patents: Paras Garg holds several patents in the areas of artificial intelligence, machine learning, and renewable energy technologies, showcasing his innovative mindset and forward-thinking approach.

Career Highlights: With a background in engineering and a passion for creating solutions to real-world problems, Paras Garg has successfully developed and patented inventions that have the potential to shape the future of various industries.

Collaborations: Throughout his career, Paras Garg has collaborated with leading tech companies, research institutions, and universities to further enhance his inventions and bring them to the market, solidifying his reputation as a respected innovator in the field.

Conclusion: Paras Garg's dedication to innovation and his relentless pursuit of excellence continue to inspire the next generation of inventors and entrepreneurs in Noida and beyond.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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