The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 11, 2022

Filed:

Aug. 21, 2020
Applicant:

Stmicroelectronics International N.v., Geneva, CH;

Inventors:

Paras Garg, Noida, IN;

Ankit Agrawal, Greater Noida, IN;

Sandeep Kaushik, Greater Noida, IN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/0185 (2006.01); H03K 17/687 (2006.01); H03K 5/24 (2006.01);
U.S. Cl.
CPC ...
H03K 17/6874 (2013.01); H03K 5/2481 (2013.01); H03K 19/0185 (2013.01); H03K 19/018507 (2013.01);
Abstract

Low-voltage differential signaling (LVDS) receiver circuits, electronic devices, and methods are provided. A LVDS receiver includes an input differential pair of transistors that receive a differential input signal. The input differential pair includes a first NMOS transistor that receives a first input signal and a second NMOS transistor that receives a second input signal. A third NMOS transistor has source and drain terminals respectively coupled to source and drain terminals of the first NMOS transistor, and a fourth NMOS transistor has source and drain terminals respectively coupled to source and drain terminals of the second NMOS transistor. A first level shifter is coupled to a gate of the third NMOS transistor, and a second level shifter is coupled to a gate of the fourth NMOS transistor.


Find Patent Forward Citations

Loading…