The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2020

Filed:

Jul. 05, 2019
Applicant:

Stmicroelectronics International N.v., Schiphol, NL;

Inventors:

Atul Dwivedi, Benares, IN;

Paras Garg, Noida, IN;

Kallol Chatterjee, Kolkata, IN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/007 (2006.01); H03K 19/0185 (2006.01); G01R 31/317 (2006.01);
U.S. Cl.
CPC ...
H03K 19/018528 (2013.01); G01R 31/31706 (2013.01);
Abstract

A low-voltage-differential-signaling (LVDS) fault detector includes first and second LVDS lines, and a window comparator provides a first output indicating whether a difference between voltages at the first and second LVDS lines is greater than a threshold voltage, and a second output indicating whether a difference between the voltages at the second and first LVDS lines is greater than the threshold voltage. A charge circuit charges a capacitive node when either the first or second output is at a logic low, and discharges the capacitive node when neither the first nor second output is at a logic low. A Schmitt trigger generates a fault flag if charge on the capacitive node falls to a threshold.


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