Stmicroelectronics International N.v.

Stmicroelectronics Pvt. Ltd.

Stmicroelectronics (crolles 2) Sas

Paras Garg

Saiyid Mohammad Irshad Rizvi

Kallol Chatterjee

Sushil Kumar Gupta

Sandeep Kaushik

Vinod Kumar

Ankit Srivastava

Pierre Dautriche

Ravinder Kumar

Ankit Agrawal

Atul Dwivedi

Rajesh Yadav

Vinayak Agrawal

Pradeep Kumar Badrathwal

Ranjeet Kumar Gupta

Vijender Singh Chauhan

Amit Kumar Rathi

Niraj Kumar

A Low Voltage Differential Signaling (LVDS) transmitter includes driver circuit with a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistor, and a second resistor. The first transistor is coupled between a first node and first output. The second transistor is coupled between the first node and a second output. The third transistor is coupled between the first output and a second node. The fourth transistor is coupled between the second output and the second node. The first resistor is coupled between the first output and a common mode node. The second resistor is coupled between the second output and the common mode node. A pre-driver circuit generates gate control signals controlling the first, second, third, and fourth transistors in response to a data signal. A controlled timing delay is applied to the timing of logic state transistors for the control signals.

Low-voltage differential signaling (LVDS) transmitter circuit

Low-voltage differential signaling (LVDS) receiver circuits, electronic devices, and methods are provided. A LVDS receiver includes an input differential pair of transistors that receive a differential input signal. The input differential pair includes a first NMOS transistor that receives a first input signal and a second NMOS transistor that receives a second input signal. A third NMOS transistor has source and drain terminals respectively coupled to source and drain terminals of the first NMOS transistor, and a fourth NMOS transistor has source and drain terminals respectively coupled to source and drain terminals of the second NMOS transistor. A first level shifter is coupled to a gate of the third NMOS transistor, and a second level shifter is coupled to a gate of the fourth NMOS transistor.

Low current, wide range input common mode LVDS receiver devices and methods

A low-voltage-differential-signaling (LVDS) fault detector includes first and second LVDS lines, and a window comparator provides a first output indicating whether a difference between voltages at the first and second LVDS lines is greater than a threshold voltage, and a second output indicating whether a difference between the voltages at the second and first LVDS lines is greater than the threshold voltage. A charge circuit charges a capacitive node when either the first or second output is at a logic low, and discharges the capacitive node when neither the first nor second output is at a logic low. A Schmitt trigger generates a fault flag if charge on the capacitive node falls to a threshold.

Low voltage differential signaling fault detector

A drive circuit includes a first drive transistor coupled between a first supply node and an output pad of an integrated circuit and a second drive transistor coupled between a second supply node and the output pad. The first drive transistor and second drive transistors are controlled by a control signal. A body bias generator circuit is configured to apply a variable first body bias to the first transistor and a variable second body bias to the second transistor. The variable first and second body biases are generated as a function of the control signal and a voltage at the output pad.

Driver circuit including driver transistors with controlled body biasing

A circuit having a centralized PT compensation circuit to provide compensation signals to localized I/O blocks on the chip. Process variations and temperature variations tend to be approximately uniform across an integrated circuit chip. Thus, a single, centralized PT compensation circuit may be used instead of one PT compensation circuit per I/O section as with solutions of the past. Further, the PT compensation circuit may generate a digital code indicative of the effects of process and temperature. Further yet, each section of I/O block may have a local voltage compensation circuit to compensate the voltage variation of the I/O block. The voltage compensation circuit utilizes an independent reference voltage. The reference voltage is generated by the PT compensation circuit, which is placed centrally in the IC chip and hence any need to repeat the reference generation for each I/O block is eliminated.

Operating conditions compensation circuit

Skew is reduced by extracting the AC component of an input signal and superimposing it on a common reference voltage to produce a resulting voltage. The resulting voltage is provided as an input to a comparator, which compares it to the reference voltage to provide a final output. Thus, all signals fed to a system, in accordance with an embodiment, are referenced at the same DC level and hence, skew is reduced.

Reduction of signal skew

An IO buffer module optimized for a wide range of drive levels both in terms of area and performance that includes an IO cell module and at least one IO adder module operatively coupled to said IO cell module for enabling the IO buffer module for the wide range of drive levels. The IO adder module can be added with the IO cell module in a number of different combinations for providing the wide range of drive levels, and the IO buffer module can provide drive solutions from 1 mA to 10 mA or higher, in steps of 0.5 mA drive level.

Architecture for efficient usage of IO

The disclosure relates a compensated output buffer circuit providing an improved slew rate control and a method for minimizing the variations in the current slew rate of the buffer over process, voltage and temperature (PVT) conditions. The output buffer circuit includes a split-gate compensated driver and a slew rate control circuit. Accordingly, a desired slew rate can be maintained with fewer variations over wide range of variations in PVT conditions.

Compensated output buffer for improving slew control rate

An output buffer circuit for improving an output during state transitions of CMOS buffers driving transmission line loads. The circuit generates variable output impedance proportional to the load transmission line impedance. The buffer includes an output stage, such as pull up/pull down drivers for receiving an input signal and generating an output signal. The pull up/pull down drivers are biased by a circuit that generates a control signal and varies its conductivity according to the control signal. The pull up/pull down drivers initially provide a relatively low impedance to reach a desired level during the initial transition period of the output and then slowly varies its impedance in response to the control signal to suppress the ringing effect. The control circuit coupled to the input node, output node and the power supply node to generate a control signal that biases the pull up/pull down driver.

Suppressing ringing in high speed CMOS output buffers driving transmission line load

An input buffer for CMOS integrated circuits using sub-micron CMOS technology is affected by the presence of high voltage between various ports of a device. An improvement for such a buffer provides an input voltage limiting circuit making the device mode tolerant to high voltages while using low voltage tolerant CMOS devices. This improvement also reduces the switching level uncertainty due to manufacturing process variations by adding compensation devices to a first inverter stage in the input buffering stage so as to increase noise margin. A hysteresis characteristic is produced by the circuit thus reducing the effect of manufacturing process variation. The circuit can be easily interfaced to other blocks and safely operates in conjunction with relatively high voltage CMOS technology circuitry while achieving the high-speed advantage of thin gate oxide. Low power consumption is achieved by avoiding the possibility of DC current flow in the circuitry.

Input buffer for CMOS integrated circuits

Output buffers which operate at high speeds require delicate handling of the noise on the supply lines. This necessitates control be exercised over current slew rate not only on the rising edge of current but also on the falling edge of the current. A circuit provides control over the current slew rate on the falling edge in high speed output driver charging/discharging heavy load without affecting the speed of the driver (which otherwise would have created supply/ground bounce due to parasitics present in the bonding wires, package pins and on-chip metal interconnects in the I/O ring). The control circuit further suppresses the supply/ground noise by a very significant level while incurring small penalty in terms of silicon area and power dissipation. This circuit includes a CMOS circuit that is cross-coupled input connected to the output buffer input signals with a dummy capacitance coupled to the CMOS circuit output.

Low noise output buffer capable of operating at high speeds

In the present invention an apparatus and method for providing compensation against temperature, process and supply voltage variation in MOS circuits has been proposed. The invention provides a change in process, temperature and voltage detection circuit, which controls the body bias and the drive of the devices in the CMOS circuit. The detection circuit is independent of any input or internal signal of the CMOS circuit to be controlled.

Method and apparatus for providing compensation against temperature, process and supply voltage variation

The present invention provides a high-voltage tolerant input buffer circuit including a first NMOS transistor having its source terminal connected to the input pin, its gate terminal connected to a first reference voltage and its drain terminal connected to a first output terminal; a second NMOS transistor having its gate terminal connected to said first reference voltage and its source terminal connected to said first output terminal; a first PMOS transistor having its gate terminal connected to the drain terminal of said second NMOS transistor, its drain terminal connected to a second reference voltage lower than said first reference voltage and its source terminal connected to a second output terminal; a second PMOS transistor having its drain terminal connected to the drain terminal of said second NMOS transistor, its source terminal connected to said second output terminal, and its gate terminal connected to a control voltage; and a third PMOS transistor having its drain terminal connected to said second output terminal, its source terminal connected to a supply voltage, and its gate terminal connected to said control voltage.

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Noida, India

Paras Garg