IDiyas

For the Inventor, By the Inventor

Noida, India

Nityanand Rai

USPTO Granted Patents = 5

Average Co-Inventor Count = 3.3

ph-index = 1

Forward Citations = 7(Granted Patents)


Location History:

  • Delhi, IN (2017)
  • Noida, IN (2018 - 2020)
  • Uttar Pradesh, IN (2021)

Company Filing History:

goldMedal5 out of 2,542 
 
Cadence Design Systems, Inc.
 patents

Years Active: 2017-2021

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5 patents (USPTO):
1. 11100268 - Fast and accurate simulation for power delivery networks with integrated voltage regulators (2021-08-24),
2. 10552564 - Determining worst potential failure instances using full chip ESD analysis (2020-02-04),
3. 10423754 - Electrostatic discharge cell placement using effective resistance (2019-09-24),
4. 9916403 - Method and system for efficiently determining differential voltages for electrostatic discharge simulations (2018-03-13),
5. 9619604 - Electrical analysis process (2017-04-11),
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