Cadence Design Systems, Inc.

Nityanand Rai

Xin Gu

Zhiyu Zeng

Hui Zheng

Hailin Jiang

Yanfei Gu

Embodiments are generally directed to a hierarchical approach for performing simulation for PDNs that have integrated VRMs. According to certain aspects, embodiments include an approach that decouples the simulation for PDN and the simulation for VRM/PKG through PDN macromodeling. In these and other embodiments, the approach includes a SPICE-accurate simulation for the VRM part using a non-linear solver and using a linear solver for the PDN part, with minimal handshaking between them. For example, using a Backward Euler method having a fixed time step, at every simulation time interval, the linear solver sends reduced boundary currents to the non-linear solver. After the non-linear solver converges at the time interval, it sends boundary voltages back to the linear solver for determining voltages in the PDN part at the time interval.

Fast and accurate simulation for power delivery networks with integrated voltage regulators

In general, the present embodiments are directed to designing an electronic system such as an IC, and more particularly to techniques for analyzing a design for potential ESD instance failures. Embodiments allow for efficiently determining a potential ESD violation or non-violation status for a large number of instances, such as all the instances in a full chip design, by performing effective resistance analyses between all the instances and all the bumps and ESD protection devices in the design. These and other embodiments further allow for more detailed effective resistance analyses to be performed for potential failing instances.

Determining worst potential failure instances using full chip ESD analysis

In general, the present embodiments are directed to designing an electronic system such as an IC, and more particularly to a design technique that can determine an optimal number and placement of ESD cells in a design for an IC. In embodiments, the technique includes determining an effective resistance criteria between a set of candidate ESD cells to the bumps/pads of the IC and finding a minimum set of ESD cells that covers all the bumps/pads. In embodiments, the technique is employed at the early stage of the design of the IC.

Electrostatic discharge cell placement using effective resistance

An improved approach is provided for determining differential voltages for driver and receiver pairs as a result of electrostatic discharge (ESD) events including identifying circuits of interest, re-characterizing the circuits of interest into a system for evaluating differential voltages, determining the differential voltages for ESD pin locations, and outputting results after iterating through all the ESD pin locations. In some embodiments, re-characterizing may include performing a resistance only extraction of a net, attaching a resistance to any node in the circuit and to ground, formulating a conductance matrix and distributing the total current I as source points. In some embodiments, determining differential voltages for ESD pin locations may include, stamping a first ESD pin location with a total current, solving for the system using previously computed values, mapping the driver and receiver pairs to the nodes in the system, computing the differential voltage, and recording the lowest differential voltage.

Method and system for efficiently determining differential voltages for electrostatic discharge simulations

The present disclosure relates to a system and method for determining an effective electrical resistance in an electronic circuit design. Embodiments may include receiving, at one or more computing devices, an electronic circuit design and identifying one or more features associated with the electronic circuit design. Embodiments may also include performing a resistance only extraction of a circuit net associated with the electronic circuit design and identifying at least two node locations from the electronic circuit as one or more port nodes. Embodiments may further include reducing the resistance only extraction to an equivalent circuit including only the port nodes and attaching a high-resistance ground voltage source to at least one of the port nodes of the reduced equivalent circuit. Embodiments may also include generating a conductance matrix, based upon, at least in part, the reduced equivalent circuit.

Growing community of inventors

Noida, India

Nityanand Rai