The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 04, 2020
Filed:
Jun. 19, 2018
Cadence Design Systems, Inc., San Jose, CA (US);
CADENCE DESIGN SYSTEMS, INC., San Jose, CA (US);
Abstract
In general, the present embodiments are directed to designing an electronic system such as an IC, and more particularly to techniques for analyzing a design for potential ESD instance failures. Embodiments allow for efficiently determining a potential ESD violation or non-violation status for a large number of instances, such as all the instances in a full chip design, by performing effective resistance analyses between all the instances and all the bumps and ESD protection devices in the design. These and other embodiments further allow for more detailed effective resistance analyses to be performed for potential failing instances.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile