The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 24, 2021
Filed:
Aug. 29, 2017
Cadence Design Systems, Inc., San Jose, CA (US);
Zhiyu Zeng, Austin, TX (US);
Hailin Jiang, Santa Clara, CA (US);
Yanfei Gu, Austin, TX (US);
Nityanand Rai, Uttar Pradesh, IN;
Xin Gu, Austin, TX (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
Embodiments are generally directed to a hierarchical approach for performing simulation for PDNs that have integrated VRMs. According to certain aspects, embodiments include an approach that decouples the simulation for PDN and the simulation for VRM/PKG through PDN macromodeling. In these and other embodiments, the approach includes a SPICE-accurate simulation for the VRM part using a non-linear solver and using a linear solver for the PDN part, with minimal handshaking between them. For example, using a Backward Euler method having a fixed time step, at every simulation time interval, the linear solver sends reduced boundary currents to the non-linear solver. After the non-linear solver converges at the time interval, it sends boundary voltages back to the linear solver for determining voltages in the PDN part at the time interval.