Ning Chen

This inventor holds 55 USPTO granted patents and 5 published patent applications and 1 EPO patent, primarily in Memory Management (CPC class G06F). Top assignees: Micron Technology Incorporated, Seagate Technology Incorporated, Applied Materials, Inc.. Active years: 1998-2025.

USPTO Granted Patents = 55 (Patent Applications = 5)

% Patents Active = 85.5

EPO Patents = 1 (Patent Applications = 4)

Average Co-Inventor Count = 3.0

ph-index = 7

Forward Citations = 495(Granted Patents)

Forward Citations (Not Self Cited) = 480(Dec 10, 2025)

Inventors with similar research interests:

Location History:

Fremont, CA (US) (2006 - 2010)
Yorba Linda, CA (US) (1998 - 2013)
Katy, TX (US) (2018)
Cupertino, CA (US) (2018)
San Jose, CA (US) (2014 - 2024)

Company Filing History:

29 out of 39,149

Micron Technology Incorporated

patents

15 out of 8,744

Seagate Technology Incorporated

patents

4 out of 14,418

Applied Materials, Inc.

patents

4. 7 out of 834,411

Other

patents

Years Active: 1998-2025

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Areas of Expertise:

Hybrid Wear Leveling

Memory Sub-System

Data Consistency

Error Detection

Cache Memory

Non-Volatile Memory

Write Request Consolidation

Metadata Tracking

Latency Management

Data Recycling

Flash Memory

Soft-Decision Decoding

55 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 12436702 - Hybrid wear leveling for in-place data replacement media (2025-10-07),

2. 12298847 - Tracking host-provided metadata in a memory sub-system (2025-05-13),

3. 12189960 - Limiting hot-cold swap wear leveling (2025-01-07),

4. 11880600 - Consolidating write request in cache memory (2024-01-23),

5. 11874769 - Maintaining data consistency in a memory sub-system that uses hybrid wear leveling operations (2024-01-16),

6. 11861167 - Maintenance operations for memory devices (2024-01-02),

7. 11789861 - Wear leveling based on sub-group write counts in a memory sub-system (2023-10-17),

8. 11704024 - Multi-level wear leveling for non-volatile memory (2023-07-18),

9. 11698867 - Using P2L mapping table to manage move operation (2023-07-11),

10. 11687363 - Internal management traffic regulation for memory sub-systems (2023-06-27),

11. 11681472 - Unmap data pattern for coarse mapping memory sub-system (2023-06-20),

12. 11681442 - Performing hybrid wear leveling operations based on a sub-total write counter (2023-06-20),

13. 11645147 - Generating error checking data for error detection during modification of data in a memory sub-system (2023-05-09),

14. 11636008 - Tracking host-provided metadata in a memory sub-system (2023-04-25),

15. 11567825 - Generating error checking data for error detection during modification of data in a memory sub-system (2023-01-31),

Title: Inventor Ning Chen: Revolutionizing Technology in San Jose

Introduction: Ning Chen is a pioneering inventor based in San Jose, CA, known for her groundbreaking contributions to the field of technology and innovation.

Latest Patents: Chen's latest patents focus on advancements in artificial intelligence, renewable energy solutions, and sustainable technologies, showcasing her commitment to creating a more efficient and eco-friendly future.

Career Highlights: With a career spanning over two decades, Ning Chen has worked with leading tech companies in Silicon Valley, spearheading research and development projects that have resulted in numerous successful patents and inventions.

Collaborations: Chen has collaborated with top research institutions and universities to further her innovative projects, fostering a culture of creativity and knowledge-sharing within the industry.

Conclusion: Ning Chen's dedication to pushing the boundaries of technology and her passion for creating impactful solutions highlight her as a visionary inventor shaping the landscape of innovation in San Jose and beyond.