The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 27, 2023

Filed:

Apr. 22, 2020
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Fangfang Zhu, San Jose, CA (US);

Ying Yu Tai, Mountain View, CA (US);

Ning Chen, San Jose, CA (US);

Jiangli Zhu, San Jose, CA (US);

Wei Wang, Dublin, CA (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/48 (2006.01); G06F 9/50 (2006.01); G06F 9/54 (2006.01); G06F 11/30 (2006.01); G06F 11/34 (2006.01); G06F 13/16 (2006.01); G06F 5/06 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 9/4881 (2013.01); G06F 3/0659 (2013.01); G06F 5/06 (2013.01); G06F 9/5016 (2013.01); G06F 9/546 (2013.01); G06F 11/3037 (2013.01); G06F 11/3409 (2013.01); G06F 11/3433 (2013.01); G06F 13/1673 (2013.01); G06F 13/1694 (2013.01); G06F 2201/81 (2013.01); G06F 2209/5022 (2013.01);
Abstract

In one embodiment, a processing device is coupled to memory components to monitor host read operations and host write operations from a host device coupled to the plurality of memory components. The processing device schedules, using a variable size internal command queue, a predetermined proportion of back-end processing device read and write operations as internal management traffic proportional to a number of the host read operations and a number of the host write operations. The processing device then executes a subset of the host read operations and the host write operations. Following execution of the subset of the host read operations and the host write operations, the processing device executes an internal management traffic operation based on the predetermined proportion.


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