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For the Inventor, By the Inventor

Tempe, AZ, United States of America

Ned D Garinger

USPTO Granted Patents = 13

Average Co-Inventor Count = 2.9

ph-index = 9

Forward Citations = 184(Granted Patents)


Location History:

  • Chandler, AZ (US) (1992 - 1995)
  • Tempe, AZ (US) (1993 - 2007)

Company Filing History:

goldMedal8 out of 1,083 
 
Vlsi Technology, Inc.
 patents
silverMedal5 out of 5,491 
 
Freescale Semiconductor,inc.
 patents

Years Active: 1992-2007

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13 patents (USPTO):Explore Patents
1. 7277449 - On chip network (2007-10-02),
2. 7200137 - On chip network that maximizes interconnect utilization between processing elements (2007-04-03),
3. 7139860 - On chip network with independent logical and physical layers (2006-11-21),
4. 7051150 - Scalable on chip network (2006-05-23),
5. 6996651 - On chip network with memory device address decoding (2006-02-07),
6. 6145047 - Circuit and method for converting interrupt signals from level trigger (2000-11-07),
7. 5892978 - Combined consective byte update buffer (1999-04-06),
8. 5465339 - Decoupled refresh on local and system busses in a PC/at or similar (1995-11-07),
9. 5365130 - Self-compensating output pad for an integrated circuit and method (1994-11-15),
10. 5336940 - Delay-compensated output pad for an integrated circuit and method (1994-08-09),
11. 5281874 - Compensated digital delay semiconductor device with selectable output (1994-01-25),
12. 5252867 - Self-compensating digital delay semiconductor device with selectable (1993-10-12),
13. 5136180 - Variable frequency clock for a computer system (1992-08-04),

Title: The Innovative Mind of Ned D. Garinger

Introduction

Ned D. Garinger is a prominent inventor based in Tempe, AZ (US). He has made significant contributions to the field of integrated processing elements, holding a total of 13 patents. His work focuses on enhancing the efficiency and functionality of on-chip networks.

Latest Patents

Garinger's latest patents include groundbreaking technologies such as an on-chip network designed for integrated processing elements. This network features multiple ports and port interfaces that adhere to a consistent port protocol. Each port interface is responsible for converting information between bus transactions of corresponding processing elements and network packets. The system is designed to maximize interconnect utilization, ensuring efficient data transfer between processing elements. The network includes an interconnect and an arbiter, which manages transaction requests and optimizes data paths to minimize dead cycles.

Career Highlights

Throughout his career, Garinger has worked with notable companies such as VLSI Technology, Inc. and Freescale Semiconductor, Inc. His experience in these organizations has allowed him to develop and refine his innovative ideas, contributing to advancements in technology.

Collaborations

Garinger has collaborated with talented individuals in the field, including Martin L. Dorr and Mark W. Naumann. These partnerships have fostered a creative environment that has led to the development of cutting-edge technologies.

Conclusion

Ned D. Garinger is a distinguished inventor whose work in integrated processing elements and on-chip networks has made a lasting impact on the technology landscape. His innovative patents and collaborations highlight his commitment to advancing the field.

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