Self-compensating digital delay semiconductor device with selectable

Abstract

A self-compensated digital delay semiconductor device is disclosed which uses two identical chains of delay elements. The first chain is the Reference Chain, which is driven by a crystal-controlled digital clock input. The second chain is the Input Signal Delay Chain, which is the delay path for the signal of interest. These two chains are located in physical proximity on the semiconductor die so that variations in manufacturing process, temperature and power supply affect each chain the same. Each of these delay chains is comprised of a series of variable delay elements which are digitally controlled by Monitor Logic, which measures the delay performance of the Reference Chain, and dynamically adjusts the delay of the variable delay elements as induced variations are induced, thereby compensating the delay of the device. Any one of these precise delays can be routed to the output by driving a tap select multiplexer to select the delay of interest. This approach provides precise delays which are constant within a tight tolerance.